Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

i#1569 AArch64: Follow-up to 3275b81: check X30 opnd in encoder. #2515

Merged
merged 2 commits into from
Jul 10, 2017
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 6 additions & 4 deletions core/arch/aarch64/codec.c
Original file line number Diff line number Diff line change
Expand Up @@ -1195,7 +1195,7 @@ encode_opnd_imms(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
return encode_opnd_imm_bf(10, enc, opnd, enc_out);
}

/* impx30: implicit X30 operand, used by BLR. */
/* impx30: implicit X30 operand, used by BLR */

static inline bool
decode_opnd_impx30(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
Expand Down Expand Up @@ -2363,10 +2363,12 @@ decode_opnds_b(uint enc, dcontext_t *dcontext, byte *pc, instr_t *instr, int opc
static inline uint
encode_opnds_b(byte *pc, instr_t *instr, uint enc)
{
uint off;
if (((instr_get_opcode(instr) == OP_bl && instr_num_dsts(instr) == 1) ||
instr_num_dsts(instr) == 0) &&
int opcode = instr_get_opcode(instr);
bool is_bl = (opcode == OP_bl);
uint off, x30;
if (instr_num_dsts(instr) == (is_bl ? 1 : 0) &&
instr_num_srcs(instr) == 1 &&
(!is_bl || encode_opnd_impx30(enc, opcode, pc, instr_get_dst(instr, 0), &x30)) &&
encode_pc_off(&off, 26, pc, instr, instr_get_src(instr, 0)))
return (enc | off);
return ENCFAIL;
Expand Down
2 changes: 1 addition & 1 deletion core/arch/aarch64/codec.txt
Original file line number Diff line number Diff line change
Expand Up @@ -258,7 +258,7 @@ x0110111xxxxxxxxxxxxxxxxxxxxxxxx tbnz tbz
## Unconditional branch (register)

1101011000011111000000xxxxx00000 br : x5
1101011000111111000000xxxxx00000 blr impx30: x5
1101011000111111000000xxxxx00000 blr impx30 : x5
1101011001011111000000xxxxx00000 ret : x5

# Loads and Stores
Expand Down