Skip to content
View GauravSingh789's full-sized avatar
💭
Processing
💭
Processing

Highlights

  • Pro

Organizations

@spider-tronix
Block or Report

Block or report GauravSingh789

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. Cascaded-SVM-on-FPGA Cascaded-SVM-on-FPGA Public

    Implementing a cascaded SVM on FPGA

    Verilog 6 2

  2. spider-tronix/VLSI spider-tronix/VLSI Public archive

    RISC V core implementation using Verilog.

    Verilog 23 4

  3. e-Yantra-Robotics-Competition e-Yantra-Robotics-Competition Public

    Forked from sachin-101/e-Yantra-Robotics-Competition

    E-Yantra 2019-20. Theme : Supply Bot

    Python

  4. Customizing_RISC_V Customizing_RISC_V Public

    Implementing ORB Feature detection algorithm on RISC-V Core

    Verilog 4 2

  5. Digital-Clock-with-I2C-Protocol Digital-Clock-with-I2C-Protocol Public

    RTC (Real Time Clock) module interfaced with Atmega 328p micro-controller.

    C++

  6. AVR-Piano AVR-Piano Public

    Musical notes generated using PWM in Atmega 328p Microcontroller

    C++ 2