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Studying Electronics and communication Engineering at NIT Trichy
- Tiruchirappalli, Tamil Nadu , India
- https://www.linkedin.com/in/gaurav-singh-0b056117b
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spider-tronix/VLSI
spider-tronix/VLSI Public archiveRISC V core implementation using Verilog.
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e-Yantra-Robotics-Competition
e-Yantra-Robotics-Competition PublicForked from sachin-101/e-Yantra-Robotics-Competition
E-Yantra 2019-20. Theme : Supply Bot
Python
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Customizing_RISC_V
Customizing_RISC_V PublicImplementing ORB Feature detection algorithm on RISC-V Core
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Digital-Clock-with-I2C-Protocol
Digital-Clock-with-I2C-Protocol PublicRTC (Real Time Clock) module interfaced with Atmega 328p micro-controller.
C++
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