Update SEGASYS1_MAIN.v

Gehstock · Jun 30, 2021 · ead26d0 · ead26d0
1 parent cfbe30b
commit ead26d0
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v
@@ -51,7 +51,7 @@ end
 wire      CPUCL_EN = CLK4M_EN;
 
 wire  [7:0]	CPUDI;
-wire			CPURD;
+//wire			CPURD;
 
 wire	cpu_m1;
 wire	cpu_mreq, cpu_iorq;
@@ -74,7 +74,7 @@ Z80IP maincpu(
 );
 
 assign CPUWR = _cpu_wr & cpu_mreq;
-assign CPURD = _cpu_rd & cpu_mreq;
+//assign CPURD = _cpu_rd & cpu_mreq;
 
 
 // Input Port