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Smith_Waterman_ASIC

The aim of this project is to implement a Smith-Waterman accelerator with 256 PEs.

This is the final project of 109-1 NTUEE special project under Prof. Yi-Chang Lu's supervision.

Hardware

Hardware design reference from [1].

In order to handle longer sequence input, rather than simply making the PE array longer, I add an FIFO at the end of PE array, reducing the area cost of adding more PEs

Illustration of PE array movement with line buffer attached.

Reference

[1] Zhang, Peiheng, Guangming Tan, and Guang R. Gao. "Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform." Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07. 2007.

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