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1. Simple_UVM Simple_UVM Public

   Implements a simple UVM based testbench for a simple memory DUT.

   SystemVerilog 12 20

2. Aproximated-UVM Aproximated-UVM Public

   This repository contains a proposal UVM testbench for aproximated circuits.

   SystemVerilog 4

3. UVM-APB_RAL UVM-APB_RAL Public

   This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.

   SystemVerilog 33 20

4. Posits_Arithmetics Posits_Arithmetics Public

   Provides a Hardware Description of basics arithmetics on posit format.

   SystemVerilog 3 1

5. axi4lite2uart axi4lite2uart Public

   This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.

   SystemVerilog 17 3

6. UVM_Python UVM_Python Public

   This repository contains an example of the connection between an UVM Testbench and a Python reference model.

   SystemVerilog 7