wannabe-CPU

An early version of a CPU, it's likely a hybrid between CISC and RISC architectures.

building and simulating

This project is meant to be simulated with iverilog and displayed with gtkwave.

Included with the project in /programs are .asm fils, these are the CPUs ROM and they can be assembled using simple-assembler.sh. (depends on sed)

After that's done, to execute the simulation and visualization run the save file ./output/save or manually use iverilog and gtkwave. Keep in mind that testbench uses the LXT2 format instead of the default VCD, this requires an additional -lxt2 flag in vvp. You'll also need to include every single verilog file located in src/ and selected testbench from tb/.

All scripts are meant to be executed from the root of the project, not from inside of the output directory.

tips

• The project includes inst_filter.gtkw file, which can be used in gtkwave to replace 5-bit entries containing opcodes to mnemonic representation of the instruction.
• Both scripts (iverilog-run and ./output/save) can be appended with -q flag to execute them without launching gtkwave, then an existing gtkwave instance can be refreshed with CTRL + SHIFT + R
• Gtkwave itself can save signal arrangement with CTRI + S key combination.

TODO

• Carry support
• Add a simple jump
• Conditional jump
• Relative jump
• Jumps from register value
• Calls and returns
• Negative numbers (two's complement)
• Turns out internal RST doesn't work, fix it
• Move ROM outside of the core.v
• Pipeline