AltairX

New computer and new CPU.

The main processor of the AltairX is a VLIW In Order CPU.
It has 4 internal memory:

64 KiB L1 instruction Cache 4-way.
32 KiB L1 data Cache RW 4-way.
32 KiB L1 data Cache R 4-way.
16 KiB L1 data Scratchpad memory.

Algorithms cache used is MRU based Pseudo LRU (PLRUm).
If used 2-way Algorithms cache used is FIFO.

The processor has no branch prediction.

The number of instructions is done via a "Pairing" bit, when it is equal to 1, there is another instruction to be executed in parallel, 0 indicates the end of the bundle.

The goal of this processor is to achieve the minimum CPU latency, and to solve the RAM latency problem. To do this, the compiler will have to do two things:

resolve pipeline conflicts
indicate the instructions to be executed in parallel
optimize pipeline
prefetch instruction and data
use SPM

The processor has 54 general registers of 64 bits, and 54 registers of 64 bits for the FPU. It has 8 additional special registers: Zero, and 6 for bypass

It has 140 instructions distributed like this:
ALU : 32
LSU : 12
BRU : 20
FPU : 16x3
EFU : 16
MDU : 6 CU : 4

For floating point numbers in AltairX , it will not be 100% compatible with the standard with IEEE 754
-Non-normalized numbers are not handled (they are equal to zero).
-Infinite numbers cannot be handled (they are worth the max value).
-NaN values are not manage (they are worth the max value).
-Rounding is always towards 0
-Exceptions are not handled

The advantage of this processor is that it has a simple design, and requires little transistor for "high performance" and therefore consume / cost less than CISC/RISC Out Of Order processors.