The pipelined CPU written in verilog.
ISE 14.7
Sword-v4
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Structural Hazard
Double-bump
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Data Hazard
bypass
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Control Hazard
time slot
A script to transform "debug.txt" into "debug.hex" which stores in VRAM.
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KathyFlores/PipelinedCPU
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A pipelinedCPU written in verilog.
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