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PipelinedCPU


The pipelined CPU written in verilog.

Environment

ISE 14.7

Sword-v4

Technique to resolve the hazard

  • Structural Hazard

    Double-bump

  • Data Hazard

    bypass

  • Control Hazard

    time slot

Debugger

A script to transform "debug.txt" into "debug.hex" which stores in VRAM.

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A pipelinedCPU written in verilog.

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