cache-prefetch-whitelist

[cmcantalupo]

@slabasan @rountree @bensallen @sssylvester

The article below:

https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors

describes the use of MSR offset 0x1A4 bits 0-3 to enable/disable hardware prefetching. Can LLNL verify the safety of these bits and open them in the whitelist maintained in the msr-safe repo?

Thanks,
Chris