vhdl/nvc: terminate nvc simulation with report severity error end of …

…test
Martoni · Aug 29, 2023 · 180d108 · 180d108
1 parent c01bff7
commit 180d108
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/vhdl/Makefile b/vhdl/Makefile
@@ -19,7 +19,7 @@ nvc_button_deb:  test/test_$(PROJECT_NAME).vhd src/$(PROJECT_NAME).vhd
 	mkdir -p nvc$(SIMU_DIR)
 	cd nvc$(SIMU_DIR); $(NVC) -a ../test/test_$(PROJECT_NAME).vhd ../src/$(PROJECT_NAME).vhd
 	cd nvc$(SIMU_DIR); $(NVC) -e $(PROJECT_NAME)_tb
-	cd nvc$(SIMU_DIR); $(NVC) -r $(PROJECT_NAME)_tb -w
+	cd nvc$(SIMU_DIR); $(NVC) -r $(PROJECT_NAME)_tb -w --exit-severity=error
 
 nvc_view: $(SIMU_DIR)/$(PROJECT_NAME)_tb.fst
 	$(WAVE) $^

diff --git a/vhdl/test/test_button_deb.vhd b/vhdl/test/test_button_deb.vhd
@@ -111,7 +111,8 @@ begin
         end loop;
         report "<- Simulation Time";
         wait for 1 ns;
-        assert false report "*** End of test ***";
+        -- old fashion way to terminate bench.
+        assert false report "*** End of test ***" severity error;
     end process stimulis_p;
 
 end Architecture button_deb_tb_1 ;