mv_ddr: ddr3: fix tRAS timimg parameter #15
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Based on the JEDEC standard JESD79-3F. The tRAS timings should include the highest speed bins at a given frequency. This is similar to commit 683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong comparison was used in the initial implementation. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
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Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[MarvellEmbeddedProcessors/mv-ddr-marvell#15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This pull request was already merged by commit da110088dd35f589374d02f926a1109c5c11a020 into mv-ddr-devel branch. |
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Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the
wrong comparison was used in the initial implementation.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz