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xilinx-sv

SystemVerilog component lib

TO DO

  1. Add documentation for

    • axi checker
    • axi dump gen
    • axi memory writer
    • axi mm perf counter
    • axis uart bridge
    • axis fir filter
  2. Fix issue with fir filter accumulator synthesizes to LUT&FF, but should in DSP

  3. Add coefficients load interface for fir filter

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SystemVerilog component lib

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