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Restore Ladder Effect and Audio Balance after update to jt12/jt89 #210

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Restore Ladder Effect and Audio Balance after update to jt12/jt89 #210

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2 changes: 1 addition & 1 deletion Genesis.sv
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Expand Up @@ -278,7 +278,7 @@ localparam CONF_STR = {
"P1OA,CRAM Dots,Off,On;",
"P1-;",
"P1OEF,Audio Filter,Model 1,Model 2,Minimal,No Filter;",
//"P1OB,FM Chip,YM2612,YM3438;",
"P1OB,FM Chip,YM2612,YM3438;",
"P1ON,HiFi PCM,No,Yes;",

"P2,Input;",
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2 changes: 2 additions & 0 deletions rtl/jt12/jt12.v
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Expand Up @@ -35,6 +35,7 @@ module jt12 (
output irq_n,
// configuration
input en_hifi_pcm,
input ladder,
// combined output
output signed [15:0] snd_right,
output signed [15:0] snd_left,
Expand All @@ -55,6 +56,7 @@ jt12_top u_jt12(
.irq_n ( irq_n ),
// configuration
.en_hifi_pcm ( en_hifi_pcm ),
.ladder ( ladder ),
// Unused ADPCM pins
.adpcma_addr ( ), // real hardware has 10 pins multiplexed through RMPX pin
.adpcma_bank ( ),
Expand Down
46 changes: 25 additions & 21 deletions rtl/jt12/jt12_acc.v
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Expand Up @@ -37,6 +37,8 @@ module jt12_acc(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input ladder,
input channel_en,
input signed [8:0] op_result,
input [ 1:0] rl,
input zero,
Expand All @@ -49,8 +51,8 @@ module jt12_acc(
input pcm_en, // only enabled for channel 6
input signed [8:0] pcm,
// combined output
output reg signed [11:0] left,
output reg signed [11:0] right
output reg signed [15:0] left,
output reg signed [15:0] right
);

reg sum_en;
Expand All @@ -72,36 +74,38 @@ always @(posedge clk) if(clk_en)

wire use_pcm = ch6op && pcm_en;
wire sum_or_pcm = sum_en | use_pcm;
wire left_en = rl[1];
wire right_en= rl[0];
// wire left_en = rl[1];
// wire right_en= rl[0];
wire signed [8:0] pcm_data = pcm_sum ? pcm : 9'd0;
wire [8:0] acc_input = use_pcm ? pcm_data : op_result;

wire signed [8:0] acc_input = ~channel_en ? 9'd0 : (use_pcm ? pcm_data : op_result);

// Continuous output
wire signed [11:0] pre_left, pre_right;
jt12_single_acc #(.win(9),.wout(12)) u_left(
wire signed [8:0] acc_out;
jt12_single_acc #(.win(9),.wout(9)) u_acc(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( acc_input ),
.sum_en ( sum_or_pcm & left_en ),
.sum_en ( sum_or_pcm ),
.zero ( zero ),
.snd ( pre_left )
.snd ( acc_out )
);

jt12_single_acc #(.win(9),.wout(12)) u_right(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( acc_input ),
.sum_en ( sum_or_pcm & right_en ),
.zero ( zero ),
.snd ( pre_right )
);
wire signed [15:0] acc_expand = {{7{acc_out[8]}}, acc_out};

reg [1:0] rl_latch, rl_old;

wire signed [4:0] ladder_left = ~ladder ? 5'd0 : (acc_expand >= 0 ? 5'd7 : (rl_old[1] ? 5'd0 : -5'd6));
wire signed [4:0] ladder_right = ~ladder ? 5'd0 : (acc_expand >= 0 ? 5'd7 : (rl_old[0] ? 5'd0 : -5'd6));

// Output can be amplied by 8/6=1.33 to use full range
// an easy alternative is to add 1/4th and get 1.25 amplification
always @(posedge clk) if(clk_en) begin
left <= pre_left + { {2{pre_left [11]}}, pre_left [11:2] };
right <= pre_right + { {2{pre_right[11]}}, pre_right[11:2] };
if (channel_en)
rl_latch <= rl;
if (zero)
rl_old <= rl_latch;

left <= rl_old[1] ? acc_expand + ladder_left : ladder_left;
right <= rl_old[0] ? acc_expand + ladder_right : ladder_right;
end

endmodule
28 changes: 20 additions & 8 deletions rtl/jt12/jt12_top.v
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Expand Up @@ -32,6 +32,7 @@ module jt12_top (
input [1:0] addr,
input cs_n,
input wr_n,
input ladder,

output [7:0] dout,
output irq_n,
Expand Down Expand Up @@ -273,7 +274,7 @@ end else begin : gen_adpcm_no
end
endgenerate

/* verilator tracing_on */
/* verilator tracing_off */
jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
// .rst_n ( rst_n ),
.clk ( clk ), // CPU clock
Expand All @@ -288,7 +289,7 @@ jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
);


/* verilator tracing_on */
/* verilator tracing_off */
jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm))
u_mmr(
.rst ( rst ),
Expand Down Expand Up @@ -396,7 +397,7 @@ jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_a
.div_setting(div_setting)
);

/* verilator tracing_on */
/* verilator tracing_off */
// YM2203 seems to use a fixed cen/3 clock for the timers, regardless
// of the prescaler setting
wire timer_cen = fast_timers ? cen : clk_en;
Expand Down Expand Up @@ -490,7 +491,7 @@ endgenerate
wire [ 8:0] op_result;
wire [13:0] op_result_hd;
`ifndef NOFM
/* verilator tracing_on */
/* verilator tracing_off */
jt12_pg #(.num_ch(num_ch)) u_pg(
.rst ( rst ),
.clk ( clk ),
Expand Down Expand Up @@ -579,11 +580,17 @@ assign op_result_hd = 'd0;
`endif

/* verilator tracing_on */
genvar i;
wire signed [15:0] accum_r[7];
wire signed [15:0] accum_l[7];

assign fm_snd_left = accum_l[0] + accum_l[1] + accum_l[2] + accum_l[4] + accum_l[5] + accum_l[6];
assign fm_snd_right = accum_r[0] + accum_r[1] + accum_r[2] + accum_r[4] + accum_r[5] + accum_r[6];

generate
if( use_pcm==1 ) begin: gen_pcm_acc // YM2612 accumulator
assign fm_snd_right[3:0] = 4'd0;
assign fm_snd_left [3:0] = 4'd0;
// assign fm_snd_right[3:0] = 4'd0;
// assign fm_snd_left [3:0] = 4'd0;
assign snd_sample = zero;
reg signed [8:0] pcm2;

Expand Down Expand Up @@ -627,10 +634,13 @@ generate
assign pcm2 = pcm;
`endif

for (i = 0; i < 7; i = i + 1) begin : accumulator_block
jt12_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.channel_en (cur_ch == i),
.ladder ( ladder ),
.op_result ( op_result ),
.rl ( rl ),
// note that the order changes to deal
Expand All @@ -645,9 +655,11 @@ generate
.pcm ( pcm2 ),
.alg ( alg_I ),
// combined output
.left ( fm_snd_left [15:4] ),
.right ( fm_snd_right[15:4] )
.left ( accum_l[i]),
.right ( accum_r[i])
);
end

end
if( use_pcm==0 && use_adpcm==0 ) begin : gen_2203_acc // YM2203 accumulator
wire signed [15:0] mono_snd;
Expand Down
6 changes: 3 additions & 3 deletions rtl/system.sv
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Expand Up @@ -1402,13 +1402,13 @@ jt12 fm
.din(ZBUS_DO),
.dout(FM_DO),
.en_hifi_pcm( EN_HIFI_PCM ),
//.ladder(LADDER),
.ladder(LADDER),
.snd_left(FM_left),
.snd_right(FM_right)
);

wire signed [15:0] fm_adjust_l = FM_left; //(FM_left << 4) + (FM_left << 2) + (FM_left << 1) + (FM_left >>> 2);
wire signed [15:0] fm_adjust_r = FM_right; //(FM_right << 4) + (FM_right << 2) + (FM_right << 1) + (FM_right >>> 2);
wire signed [15:0] fm_adjust_l = (FM_left << 4) + (FM_left << 2) + (FM_left << 1) + (FM_left >>> 2);
wire signed [15:0] fm_adjust_r = (FM_right << 4) + (FM_right << 2) + (FM_right << 1) + (FM_right >>> 2);

genesis_fm_lpf fm_lpf_l
(
Expand Down