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NetFPGA SUME Reference Learning Switch Lite Vivado 2020.1 and Ubuntu 2020.4

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Salvator Galea edited this page Jul 12, 2021 · 2 revisions

Name

reference_switch_lite

Location

projects/reference_switch_lite

IP Cores

Software

Description

The division of the hardware into modules was hinted at in the previous section. Understanding these modules is essential in making the most of the available designs. The reference projects in NetFPGA platform, including the Switch Lite, all follow the same modular structure. This design is a pipeline where each stage is a separate module.

Packets first enter the device through the nf_10g_interface module, which is an IP that combines Xilinx AXI 10G Ethernet subsystem, in addition to an AXI4-Stream adapter. There are 4 such module instances in the design, one per port. The packets arriving from the external SFP ports are processed by the PMA and PCS parts of the 10G Ethernet core, are next read in by Xilinx 10G MAC (within the same core). Every incoming packet is annotated with metadata and is finally transformed into 256-bit AXI4-Stream. The TX side follows the exact same path but in the opposite direction.

The nf_10g_interface modules RX connect next to the input arbiter module. The input arbiter has four input interfaces: four from the nf_10g_interface modules and one from a DMA module (to be described later on). Each input to the arbiter connects to an input queue, which is in fact a small fall-through FIFO. The simple arbiter rotates between all the input queues in a round robin manner, each time selecting a non-empty queue and writing one full packet from it to the next stage in the data-path, which is the output port lookup module.

The output port lookup module is responsible for deciding which port a packet goes out of. After that decision is made, the packet is then handed to the output queues module. The lookup module implements a simple learning CAM, implemented using registers. Packets with unknown destination MAC address are broadcasted.

Once a packet arrives to the output_queues module, it already has a marked destination (provided on a side channel - The TUSER field). According to the destination it is entered to a dedicated output queue. There are five such output queues: one per each 10G port and one to the DMA block. Note that a packet may be dropped if its output queue is full or almost full. When a packet reaches the head of its output queue, it is sent to the corresponding output port, being either an nf_10g_interface module or the DMA module. The output queues are arranged in an interleaved order: one physical Ethernet port, one DMA port etc. Even queues are therefore assigned to physical Ethernet ports, and odd queues are assigned to the virtual DMA ports.

The DMA module serves as a DMA engine for the reference switch design. It includes Xilinx' PCIe core, a DMA engine and AXI4 Interconnect module. To the other NetFPGA modules it exposes AXIS (master+slave) interfaces for sending/receiving packets, as well as a AXI4-LITE master interface through which all AXI registers can be accessed from the host (over PCIe). To this end it connects to the axi_interconnect module. In the Reference Switch Lite design the DMA module is used only for register access.

The reference Switch Lite design implements a Xilinx Microblaze subsystem, including also a BRAM memory block and its controller. This module is currently used only for clock configuration. For more information, please refer to the Microblaze reference links provided above.

Latency

The average port-to-port latency of the switch is 823ns. Most of the latency is contributed by the 10GE Ethernet port. Refer to Xilinx PG157 for more details on 10GE port IP.

Testing

  1. Make sure you clone the latest version of the NetFPGA package. Please ensure that you have the necessary packages installed. The current testing infrastructure is Python based.
git clone https://github.com/NetFPGA/NetFPGA-SUME-live.git
  1. Make sure to update the following environment variables in the file {user-path}/NetFPGA-SUME-live/tools/settings.sh
  • SUME_FOLDER
  • XILINX_PATH
  • VITIS_PATH
  • NF_PROJECT_NAME

To set the environment variables, source both relevant setting files:

source {user-path}/NetFPGA-SUME-live/tools/settings.sh
source $XILINX_PATH/settings64.sh
  1. Compile the library of IP cores. (It is unnecessary to compile the library every time for a new project unless you have made any changes to the IP cores.)
[user@nf-test109 ~]# cd $SUME_FOLDER 
[user@nf-test109 NetFPGA-SUME-live]# make
  1. Program the FPGA
  • If you want to run the Hardware tests with the pre-existing bitfile provided in the base repo:
cd $NF_DESIGN_DIR/bitfiles
[user@nf-test109 bitfiles]# xsct

On the xsct console, use connect and then fpga -f reference_switch_lite.bit to program the FPGA with the bitfile and exit to close xsct console. Reboot the machine.

  • If you want to create your own bitfile and run the Hardware tests:
cd $NF_DESIGN_DIR
[user@nf-test109 reference_switch_lite]# make
[user@nf-test109 reference_switch_lite]# cd bitfiles
[user@nf-test109 bitfiles]# xsct

On the xsct console, use connect and then fpga -f reference_switch_lite.bit to program the FPGA with the bitfile and exit to close xsct console. Reboot the machine.

  1. Check if the bitfile is loaded using the following command.
lspci –vxx | grep Xilinx

If the host machine doesn't detect the Xilinx device, you need to reprogram the FPGA and reboot as mentioned in the previous step.

  1. Build the driver for the NetFPGA SUME board.
[user@nf-test109 ~]# cd $DRIVER_FOLDER
[user@nf-test109 sume_riffa_v1_0_0]# make all
[user@nf-test109 sume_riffa_v1_0_0]# sudo make install
[user@nf-test109 sume_riffa_v1_0_0]# sudo modprobe sume_riffa

Then run ip a to check if you are able to see the 'nfX' interfaces.

  1. Running the test

The top level file nf_test.py can be found inside NetFPGA-SUME-live/tools/scripts. Tests are run using the nf_test.py command followed by the arguments indicating if it is a hardware or simulation test and what is the specific test that we would like to run. So when running the test, test mode should be specified (sim or hw). For instance:

[user@nf-test109 scripts]#./nf_test.py sim --major learning --minor sw

or

[user@nf-test109 scripts]# sudo -E env PYTHONPATH=`echo $PYTHONPATH` zsh -c 'source $XILINX_PATH/settings64.sh && ./nf_test.py hw --major simple --minor broadcast '

where -E passes set environment variables such as NF_DESIGN_DIR to sudo. Similarly env PYTHONPATH and source setting64.sh pass $PYTHONPATH (need by NFTest library) and Vivado paths to sudo. sudo is required to open a socket and to send packets through a device under test.

For a complete list of arguments type ./nf_test.py --help.

You can find more information related to hardware and simulation tests here:

The test infrastructure is based on the python. You can find the tests inside the projects/{project_name}/test folder.

Testing hardware using two or more machines

To run the test, you need two machines, A and B. Let's say Machine A is equipped with NetFPGA and Machine B is equipped with a third-party 10G dual-port NIC.

Download the reference_switch_lite bitfile from projects/reference_switch_lite/bitfiles/reference_switch_lite.bit. (Refer to Acceptance Test Manual if you don't know how to download the bitfile and/or not setup JTAG cable yet.)

Connect Machine A and Machine B using two 10G cables. Assume we use nf0 (the port farthest from the PCI Express) and nf1 on Machine A and eth1 and eth2 on Machine B. Generate packets from eth1 with given MAC addresses (let's say, dest-MAC = x and src-MAC = y). Check that all the NetFPGA physical ports send back the packet. Then, generate from eth2 packets with dest-MAC = y and src-MAC = x. You will be able to see that only nf0 will forward back packets.

Notes

  • Critical warnings of the following type should be ignored, as this is handles outside the block design: [BD 41-1348] Reset pin /dma_sub/axi_interconnect_0/M00_ARESETN (associated clock /dma_sub/axi_interconnect_0/M00_ACLK) is connected to asynchronous reset source /axis_datapath_aresetn. This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /axis_datapath_aclk.

  • Warnings of the following type should currently be ignored, it is a known issue with the block design which does not affect the functionality: [Synth 8-689] width (12) of port connection 'M00_AXI_araddr' does not match port width (32) of module 'control_sub' ["/root/NetFPGA-SUME-dev/projects/reference_switch_lite/hw/hdl/top.v":674]

  • Any questions regarding RIFFA DMA and associated warnings should be referred to the RIFFA development team. Note that the design currently uses the DMA only for register access.

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