Std. Core: 10G Ethernet Interface Shared
nf_10ge_interface_shared
v1.00
Yury Audzevich
Jong Hun Han
Noa Zilberman
IP core (HW)
lib/hw/std/cores/nf_10ge_interface_shared_v1_0_0
AXI4-Stream
AXI-Lite
M_AXIS: Master AXI4-Stream bus, Variable width - Rx Data (From the network to the host)
S_AXIS: Slave AXI4-Stream bus, Variable width - Tx Data (From the host to the network)
S_AXI: Slave AXI4-Lite
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.
C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.
C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.
C_DEFAULT_VALUE_ENABLE : Use default source and destination port values.
C_DEFAULT_SRC_PORT : Default source port value.
C_DEFAULT_DST_PORT : Default destination port value.
C_BASEADDR: Base address value of the core.
This module uses register infrastructure Ver 1.00, please refer to here for more details.
0x0 : ID - Block ID
0x4 : VERSION - Block Version
0x8 : FLIP - Returns the negative value of a written register
0xC: DEBUG - Debug register, returns the written value plus a preconfigured value
0x10: INTERFACEID - Interface Port Number
0x14 : PKTIN - Total number of incoming packets
0x18: PKTOUT - Total number of outgoing packets
0x1C: MACSTATUSVECTOR - MAC status vector
0x20: PCSPMASTATUS - PCS and PMA status vector
0x24 - 0x58: PCSPMASTATUSVECTOR0 to PCSPMASTATUSVECTOR13 - PCS and PMA 448bit status vector
The 10G Interface block receives incoming serial data from the SFP ports and converts it to a 256-bit AXI Stream interface toward the NetFPGA data path.
The block is based on the Xilinx' AXI 10G Ethernet subsystem IP. This IP includes the PMA, PCS and MAC of the 10G interface, and operates on 156.25MHz clock. The IP used in this module *includes shared logic, and is responsible to generate clocks and resets to all other 10G interfaces on the same GTH transceivers quad.
Data going out from the Xilinx's 10G subsystem, enters a 64-b data FIFO, and from there enters a submodule which adds metadata to every packet. The metadata is written into the TUSER field and includes the source and (default) destination port of a packet. Once the metadata is added, the 64b-wide AXI steam bus, is converter to 256b, matching the NetFPGA internal datapath, and the information is forwarded toward the input arbiter.
The module also includes a registers module, allowing simple debug and access to the 10G subsystem status vectors.
Xilinx AXI 10G Ethernet Subsystem
You will need a Xilinx 10G MAC license to generate this core