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NetFPGA SUME Reference NIC Vivado 2020.1 and Ubuntu 2020.4

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bmehta001 edited this page Aug 16, 2023 · 5 revisions

Name

reference_nic

Location

projects/reference_nic

IP Cores

Software

Description

The division of the hardware into modules was hinted at in the previous section. Understanding these modules is essential in making the most of the available designs. The reference projects in NetFPGA platform, including the NIC, all follow the same modular structure. This design is a pipeline where each stage is a separate module. A diagram of the pipeline is shown on the next section.

Packets first enter the device through the nf_10g_interface module, which is an IP that combines Xilinx AXI 10G Ethernet subsystem, in addition to an AXI4-Stream adapter. There are 4 such module instances in the design, one per port. The packets arriving from the external SFP ports are processed by the PMA and PCS parts of the 10G Ethernet core, are next read in by Xilinx 10G MAC (within the same core). Every incoming packet is annotated with metadata and is finally transformed into 256-bit AXI4-Stream. The TX side follows the exact same path but in the opposite direction.

The nf_10g_interface modules RX connect next to the input arbiter module. The input arbiter has five input interfaces: four from the nf_10g_interface modules and one from a DMA module (to be described later on). Each input to the arbiter connects to an input queue, which is in fact a small fall-through FIFO. The simple arbiter rotates between all the input queues in a round robin manner, each time selecting a non-empty queue and writing one full packet from it to the next stage in the data-path, which is the output port lookup module.

The output port lookup module is responsible for deciding which port a packet goes out of. After that decision is made, the packet is then handed to the output queues module. The lookup module implements a very basic lookup scheme, sending all packets from 10G ports to the CPU and vice versa, based on the source port indicated in the packet's header. Notice that although we only have one physical DMA module in Verilog, there are 4 virtual DMA ports. The virtual DMA ports are distinguished by SRC_PORT/DST_PORT field.

Once a packet arrives to the output_queues module, it already has a marked destination (provided on a side channel - The TUSER field). According to the destination it is entered to a dedicated output queue. There are five such output queues: one per each 10G port and one to the DMA block. Note that a packet may be dropped if its output queue is full or almost full. When a packet reaches the head of its output queue, it is sent to the corresponding output port, being either an nf_10g_interface module or the DMA module. The output queues are arranged in an interleaved order: one physical Ethernet port, one DMA port etc. Even queues are therefore assigned to physical Ethernet ports, and odd queues are assigned to the virtual DMA ports.

The DMA module serves as a DMA engine for the reference NIC design. It includes Xilinx' PCIe core, a DMA engine and AXI4 Interconnect module. To the other NetFPGA modules it exposes AXIS (master+slave) interfaces for sending/receiving packets, as well as a AXI4-LITE master interface through which all AXI registers can be accessed from the host (over PCIe). To this end it connects to the axi_interconnect module.

The reference NIC design implements a Xilinx Microblaze subsystem, including also a BRAM memory block and its controller. This module is currently used only for clock configuration. For more information, please refer to the Microblaze reference links provided above.

Block Diagram

Testing

  1. Make sure you clone the latest version of the NetFPGA package. Please ensure that you have the necessary packages installed. The current testing infrastructure is Python based.
git clone https://github.com/NetFPGA/NetFPGA-SUME-live.git
  1. Make sure to update the following environment variables in the file {user-path}/NetFPGA-SUME-live/tools/settings.sh
  • SUME_FOLDER
  • XILINX_PATH
  • VITIS_PATH
  • NF_PROJECT_NAME

To set the environment variables, source both relevant setting files:

source {user-path}/NetFPGA-SUME-live/tools/settings.sh
source $XILINX_PATH/settings64.sh
  1. Compile the library of IP cores. (It is unnecessary to compile the library every time for a new project unless you have made any changes to the IP cores.)
[user@nf-test109 ~]# cd $SUME_FOLDER 
[user@nf-test109 NetFPGA-SUME-live]# make
  1. Program the FPGA
  • If you want to run the Hardware tests with the pre-existing bitfile provided in the base repo:
cd $NF_DESIGN_DIR/bitfiles
[user@nf-test109 bitfiles]# xsct

On the xsct console, use connect and then fpga -f reference_nic_lite.bit to program the FPGA with the bitfile and exit to close xsct console. Reboot the machine.

  • If you want to create your own bitfile and run the Hardware tests:
cd $NF_DESIGN_DIR
[user@nf-test109 reference_nic]# make
[user@nf-test109 reference_nic]# cd bitfiles
[user@nf-test109 bitfiles]# xsct

On the xsct console, use connect and then fpga -f reference_nic_lite.bit to program the FPGA with the bitfile and exit to close xsct console. Reboot the machine.

  1. Check if the bit file is loaded using the following command.
lspci –vxx | grep Xilinx

If the host machine doesn't detect the Xilinx device, you need to reprogram the FPGA and reboot as mentioned in the previous step.

  1. Build the driver for the NetFPGA SUME board and check if the built kernel module is loaded. When building as non-root user you need to append sudo to all commands of the modules_install target.
[user@nf-test109 ~]# cd $DRIVER_FOLDER
[user@nf-test109 sume_riffa_v1_0_0]# make all
[user@nf-test109 sume_riffa_v1_0_0]# make install
[user@nf-test109 sume_riffa_v1_0_0]# modprobe sume_riffa
[user@nf-test109 sume_riffa_v1_0_0]# lsmod sume_riffa

Then run ip a to check if you are able to see the 'nfX' interfaces.

  1. Running the test

The top level file nf_test.py can be found inside NetFPGA-SUME-live/tools/scripts. Tests are run using the nf_test.py command followed by the arguments indicating if it is a hardware or simulation test and what is the specific test that we would like to run. So when running the test, test mode should be specified (sim or hw). For instance:

[user@nf-test109 scripts]#./nf_test.py sim --major loopback --minor minsize

or

[user@nf-test109 scripts]# sudo -E env PYTHONPATH=`echo $PYTHONPATH` zsh -c 'source $XILINX_PATH/settings64.sh && ./nf_test.py hw --major loopback --minor minsize '

For a complete list of arguments type ./nf_test.py --help.

You can find more information related to hardware and simulation tests here:

The test infrastructure is based on the python. You can find the tests inside the projects/{project_name}/test folder.

The 10G NIC on NetFPGA is similar to other NICs. In the following sections, we will show how to run a iperf test between NetFPGA and another machine.

Testing Hardware using two or more machines

To run the test, you need two machines, A and B. Let's say Machine A is equipped with NetFPGA and Machine B is equipped with a third-party 10G NIC.

Download the reference_nic bitfile from projects/reference_nic/bitfiles/reference_nic.bit. (Refer to Hardware Tests if you don't know how to download the bitfile and/or not setup JTAG cable yet.)

Connect Machine A and Machine B using a 10G cable. Assume we use nf0 (the port farthest from the PCI Express) on Machine A and eth1 on Machine B.

Build and Install the NetFPGA-SUME NIC Driver

Here is a Quick Start.

Setup IP address

On Machine A

    sudo ip addr add 192.168.0.1 dev nf0

On Machine B

    sudo ip addr add 192.168.0.2 dev nf0

Test 1: Ping

On Machine A

    [user@machine_A ~]$ ping 192.168.0.2
    PING 192.168.0.2 192.168.0.2) 56(84) bytes of data.
    64 bytes from 192.168.0.2: icmp_req=1 ttl=50 time=1.04 ms
    64 bytes from 192.168.0.2: icmp_req=2 ttl=50 time=1.04 ms
    64 bytes from 192.168.0.2: icmp_req=3 ttl=50 time=1.04 ms
    64 bytes from 192.168.0.2: icmp_req=4 ttl=50 time=1.04 ms

Test 2: iperf

iperf is a utility to measure the performance over an IP link.

First, make sure you have iperf installed on both machines. If not,

sudo apt install iperf

Setup iperf server on Machine A.

iperf -s

Setup iperf client on Machine B.

    [user@machine_B ~]$ iperf -c 192.168.0.1    
    ------------------------------------------------------------ 
    Client connecting to localhost, TCP port 5001 
    TCP window size:  132 KByte (default) 
    ------------------------------------------------------------ 
    [  3] local 192.168.0.2 port 52787 connected with 192.168.0.1 port 5001 
    [ ID] Interval       Transfer     Bandwidth 
    [  3]  0.0-10.0 sec  9.35 GBytes  935 Mbits/sec
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