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Releases: OFS/ofs-f2000x-pl

ofs-2024.1-1 Release for Agilex 7 SoC Attach Reference Shell

20 Mar 03:09
@cohensus cohensus
ofs-2024.1-1
49b5cdc
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ofs-2024.1-1 Release for Agilex 7 SoC Attach Reference Shell Latest
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OFS 2024.1-1

Summary: OFS 2024.1-1 Release for Agilex® FPGA SoC Attach shell targeting Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL

For the overall release and associated repos please review the Discussions post.
For complete documentation go to the OFS Documentation site

Details

OPAE SDK: OPAE Wiki and OPAE Installation Guide

OPAE SIM:

Driver:

This page provides up-to-date information about the Open FPGA Stack (OFS) for Agilex® SoC Attach devices. The summary of OFS framework features are shown below. To find out more about the targeted platform, please refer to the Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL .

OFS for Agilex® 7 SoC Attach Reference Design Features

Key Feature Description
PCIe P-tile PCIe* Gen4x16 to the Host
P-tile PCIe* Gen4x16 to the SoC (IceLake-D)
Virtualization Host: 2 physical functions
SoC: 1 physical function and 3 Virtual functions
Memory Four Fabric DDR4 banks, x40 (optional ECC, be configured as x32 and ECC x8 ), 1200 MHz, 4GB
Ethernet 2x4x25GbE
Configuration and Board Manageability * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration)
* Platform Controller Management Interface (PMCI) Module for Board Management Controller
Partial Reconfiguration Supported
Software Support * Linux DFL drivers targeting OFS FIMs
* OPAE Software Development Kit * OPAE Tools
Open Programmable Acceleration Engine Software (OPAE) * OPAE Software Development Kit provides support for the following OPAE user space tools:
* afu packager
* bitstreaminfo
* fpgainfo
* fpgasupdate
* host_exerciser
* hssiloopback
* hssistats
* hssimac
* mmlink
* opae.io
* opaevfio
* pacsign
* packager
* pci_device
* regmap
* debugfs
* rsu
* userclock
* vabtool

The OFS hardware framework also provides:

  • Support for unit test simulation (using Synopsys® VCS® or Siemens® Questa™ simulators)
  • UVM support with Synopsys® VCS®
  • Host exercisers that allow you to test interfaces on the FPGA

The OFS software framework provides:

  • FPGA platform Linux® drivers that are being upstreamed to linux.org
  • A programmable software development kit and userspace tools for managing the FPGA

Important: If you would like to begin evaluating the default shell that can be built from this repository, please scroll down to the "assets" accordion button below which contains the FPGA binary/POF/SOF along with the applicable Linux driver and Open Programmable Acceleration Engine (OPAE) software development kit (SDK) packages.

New Updates for ofs-2024.1-1 Release

  • Move to Quartus 23.4

Known Issues

This table describes the known issues for the 2024.1 OFS Release targeting Agilex® 7 SoC Attach devices.

IDKnown IssuesWorkaroundStatus
-All hssi tests used in unit simulation and UVM take a longer than expected time to complete.NoneFixed in future release of OFS.

Important Notes

The following section provides important information about this release:

IDImportant Notes
-When using the PF/VF configuration tool to reconfigure the PF/VF mux, you must keep at least one physical function and one virtual function on PF0. The tool does not support less than one PF and one VF on PF0. All other PFs and VFs can be removed if desired.
15012246661When enabling cable hotplug IP and ANLT, the E-tile recipe resulting from the ANLT initialization flow is over-written by the hotplug initialization flow. If you require a custom ANLT recipe, then you cannot use hotplug at this time. You can disable hotplug by writing 1 to index-0 of HSSI Hotplug Debug Control Register (offset 0x600B4) followed by a port level reset or analog reset.

Resolved Issues

There are no new resolved issues.

Assets 10
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2023.3 OFS Release for Intel Agilex 7 SoC Attach Reference Shell (ofs-2023.3)

14 Dec 05:09
@chipb-intel chipb-intel
ofs-2023.3-1
90e5abb
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2023.3 OFS Release for Intel Agilex 7 SoC Attach Reference Shell (ofs-2023.3)

OFS 2023.3

Summary: OFS 2023.3 Release for Intel® Agilex FPGA SoC Attach shell targeting Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL

OPAE SDK: OPAE Wiki and OPAE Installation Guide

OPAE SIM:

Driver:

This page provides up-to-date information about the Open FPGA Stack (OFS) for Intel® Agilex® SoC Attach devices. The summary of OFS framework features are shown below. To find out more about the targeted platform, please refer to the Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL .

Intel OFS for Intel Agilex 7 SoC Attach Reference Design Features

Key Feature Description
PCIe P-tile PCIe* Gen4x16 to the Host
P-tile PCIe* Gen4x16 to the SoC (IceLake-D)
Virtualization Host: 2 physical functions
SoC: 1 physical function and 3 Virtual functions
Memory Four Fabric DDR4 banks, x40 (optional ECC, be configured as x32 and ECC x8 ), 1200 MHz, 4GB
Ethernet 2x4x25GbE
Configuration and Board Manageability * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration)
* Platform Controller Management Interface (PMCI) Module for Board Management Controller
Partial Reconfiguration Supported
Software Support * Linux DFL drivers targeting OFS FIMs
* OPAE Software Development Kit * OPAE Tools
Open Programmable Acceleration Engine Software (OPAE) * OPAE Software Development Kit provides support for the following OPAE user space tools:
* afu packager
* bitstreaminfo
* fpgainfo
* fpgasupdate
* host_exerciser
* hssiloopback
* hssistats
* hssimac
* mmlink
* opae.io
* opaevfio
* pacsign
* packager
* pci_device
* regmap
* debugfs
* rsu
* userclock
* vabtool

The OFS hardware framework also provides:

  • Support for unit test simulation (using Synopsys® VCS® or Siemens® Questa™ simulators)
  • UVM support with Synopsys® VCS®
  • Host exercisers that allow you to test interfaces on the FPGA

The OFS software framework provides:

  • FPGA platform Linux® drivers that are being upstreamed to linux.org
  • A programmable software development kit and userspace tools for managing the FPGA

Important: If you would like to begin evaluating the default shell that can be built from this repository, please scroll down to the "assets" accordion button below which contains the FPGA binary/POF/SOF along with the applicable Linux driver and Open Programmable Acceleration Engine (OPAE) software development kit (SDK) packages.

Known Issues

This table describes the known issues for the 2023.3 OFS Release targeting Intel Agilex 7 SoC Attach devices.

IDKnown IssuesWorkaroundStatus
-All hssi tests used in unit simulation and UVM take a longer than expected time to complete.NoneFixed in future release of OFS.

Important Notes

The following section provides important information about this release:

IDImportant Notes
-When using the PF/VF configuration tool to reconfigure the PF/VF mux, you must keep at least one physical function and one virtual function on PF0. The tool does not support less than one PF and one VF on PF0. All other PFs and VFs can be removed if desired.
15012246661When enabling cable hotplug IP and ANLT, the E-tile recipe resulting from the ANLT initialization flow is over-written by the hotplug initialization flow. If you require a custom ANLT recipe, then you cannot use hotplug at this time. You can disable hotplug by writing 1 to index-0 of HSSI Hotplug Debug Control Register (offset 0x600B4) followed by a port level reset or analog reset.
15012406417If using the Intel FPGA SmartNIC N6001-PL Platform (SKU2) for evaluation of the OFS release, ensure DIP Switch SW1.4 on the board is set to convey the correct board type or the OPAE commands could display invalid temperature values for an Intel NIC E810 (SKU1) which is not populated on the SKU2 board. For Intel FPGA SmartNIC N6001-PL Platform (SKU2), SW1.4 must be off (pointing towards the PCIe goldfinger). Note that a BMC reset is required if you must flip the switch to the correct setting.

Resolved Issues

This table describes prior known issues resolved in the 2023.3 OFS Release targeting Intel Agilex 7 SoC Attach devices.

IDResolved Issues
22018273793When sending greater than 1400 byte packets upstream to the PCIe subsystem, you should disable the protocol checker in the src/top/top.sv file to prevent packet stalls.
Assets 10
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2023.2 OFS Release for Intel Agilex 7 SoC Attach Reference Shell (ofs-2023.2)

16 Sep 01:03
@cohensus cohensus
ofs-2023.2-1
f6a2bc5
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2023.2 OFS Release for Intel Agilex 7 SoC Attach Reference Shell (ofs-2023.2)

OFS 2023.2

Summary: OFS 2023.2 Release for Intel® Agilex FPGA SoC Attach shell targeting Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL

OPAE SDK: OPAE Wiki and OPAE Installation Guide

OPAE SIM:

Driver:

This page provides up-to-date information about the Open FPGA Stack (OFS) for Intel® Agilex® SoC Attach devices. The summary of OFS framework features are shown below. To find out more about the targeted platform, please refer to the Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL .

Intel OFS for Intel Agilex PCIe Attach Reference Design Features

Key Feature Description
PCIe P-tile PCIe* Gen4x16 to the Host
P-tile PCIe* Gen4x16 to the SoC (IceLake-D)
Virtualization Host: 2 physical functions
SoC: 1 physical function and 3 Virtual functions
Memory Four Fabric DDR4 banks, x40 (optional ECC, be configured as x32 and ECC x8 ), 1200 MHz, 4GB
Ethernet 2x4x25GbE
Configuration and Board Manageability * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration)
* Platform Controller Management Interface (PMCI) Module for Board Management Controller
Partial Reconfiguration Supported
Software Support * Linux DFL drivers targeting OFS FIMs
* OPAE Software Development Kit * OPAE Tools
Open Programmable Acceleration Engine Software (OPAE) * OPAE Software Development Kit provides support for the following OPAE user space tools:
* afu packager
* bitstreaminfo
* fpgainfo
* fpgasupdate
* host_exerciser
* hssiloopback
* hssistats
* hssimac
* mmlink
* opae.io
* opaevfio
* pacsign
* packager
* pci_device
* regmap
* debugfs
* rsu
* userclock
* vabtool

The OFS hardware framework also provides:

  • Support for unit test simulation (using Synopsys® VCS® or Siemens® Questa™ simulators)
  • UVM support with Synopsys® VCS®
  • Host exercisers that allow you to test interfaces on the FPGA

The OFS software framework provides:

  • FPGA platform Linux® drivers that are being upstreamed to linux.org
  • A programmable software development kit and userspace tools for managing the FPGA

Important: If you would like to begin evaluating the default shell that can be built from this repository, please scroll down to the "assets" accordion button below which contains the FPGA binary/POF/SOF along with the applicable Linux driver and Open Programmable Acceleration Engine (OPAE) software development kit (SDK) packages.

Known Issues

This table describes the known issues for the 2023.2 OFS Release targeting Intel Agilex 7 SoC Attach devices.

IDKnown IssuesWorkaroundStatus
22018273793When sending greater than 1400 byte packets upstream to the PCIe subsystem, you should disable the protocol checker in the src/top/top.sv file to prevent packet stalls.NoneFixed in a future version of OFS.
-All hssi tests used in unit simulation and UVM take a longer than expected time to complete.NoneFixed in future release of OFS.

Important Notes

The following section provides important information about this release:

IDImportant Notes
-When using the PF/VF configuration tool to reconfigure the PF/VF mux, you must keep at least one physical function and one virtual function on PF0. The tool does not support less than one PF and one VF on PF0. All other PFs and VFs can be removed if desired.
15012246661When enabling cable hotplug IP and ANLT, the E-tile recipe resulting from the ANLT initialization flow is over-written by the hotplug initialization flow. If you require a custom ANLT recipe, then you cannot use hotplug at this time. You can disable hotplug by writing 1 to index-0 of HSSI Hotplug Debug Control Register (offset 0x600B4) followed by a port level reset or analog reset.
15012406417If using the Intel FPGA SmartNIC N6001-PL Platform (SKU2) for evaluation of the OFS release, ensure DIP Switch SW1.4 on the board is set to convey the correct board type or the OPAE commands could display invalid temperature values for an Intel NIC E810 (SKU1) which is not populated on the SKU2 board. For Intel FPGA SmartNIC N6001-PL Platform (SKU2), SW1.4 must be off (pointing towards the PCIe goldfinger). Note that a BMC reset is required if you must flip the switch to the correct setting.

Resolved Issues

This table describes prior known issues resolved in the 2023.2 OFS Release targeting Intel Agilex 7 SoC Attach devices.

IDResolved Issues
14017669281The version of cable hotplug IP in this release supports the VSR (very short route) recipes only.
14019349213he_random_long_test and mmio_stress_test generate mmio_timeout_errors.
14019381876The ofs-f2000x reference design does not have the Ethernet link and status LED logic enabled to work with the Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL
Assets 11
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2023.1 OFS Release for Intel Agilex SoC Attach Reference Shell (ofs-2023.1)

26 May 20:59
@michelleyho michelleyho
ofs-2023.1-1
4bf5b5b
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2023.1 OFS Release for Intel Agilex SoC Attach Reference Shell (ofs-2023.1)

OFS 2023.1

Summary: OFS 2023.1 Release for Intel® Agilex FPGA SoC Attach shell targeting Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL

OPAE SDK: OPAE Wiki and OPAE Installation Guide

OPAE SIM:

Driver:

This page provides up-to-date information about the Open FPGA Stack (OFS) for Intel® Agilex® SoC Attach devices. The summary of OFS framework features are shown below. To find out more about the targeted platform, please refer to the Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL .

Intel OFS for Intel Agilex PCIe Attach Reference Design Features

Key Feature Description
PCIe P-tile PCIe* Gen4x16 to the Host
P-tile PCIe* Gen4x16 to the SoC (IceLake-D)
Virtualization Host: 2 physical functions
SoC: 1 physical function and 3 Virtual functions
Memory Four Fabric DDR4 banks, x40 (optional ECC, be configured as x32 and ECC x8 ), 1200 MHz, 4GB
Ethernet 2x4x25GbE
Configuration and Board Manageability * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration)
* Platform Controller Management Interface (PMCI) Module for Board Management Controller
Partial Reconfiguration Supported
Software Support * Linux DFL drivers targeting OFS FIMs
* OPAE Software Development Kit * OPAE Tools
Open Programmable Acceleration Engine Software (OPAE) * OPAE Software Development Kit provides support for the following OPAE user space tools:
* afu packager
* bitstreaminfo
* fpgainfo
* fpgasupdate
* host_exerciser
* hssiloopback
* hssistats
* hssimac
* mmlink
* opae.io
* opaevfio
* pacsign
* packager
* pci_device
* regmap
* debugfs
* rsu
* userclock
* vabtool

The OFS hardware framework also provides:

  • Support for unit test simulation (using Synopsys® VCS® or Siemens® Questa™ simulators)
  • UVM support with Synopsys® VCS®
  • Host exercisers that allow you to test interfaces on the FPGA

The OFS software framework provides:

  • FPGA platform Linux® drivers that are being upstreamed to linux.org
  • A programmable software development kit and userspace tools for managing the FPGA

Important: If you would like to begin evaluating the default shell that can be built from this repository, please scroll down to the "assets" accordion button below which contains the FPGA binary/POF/SOF along with the applicable Linux driver and Open Programmable Acceleration Engine (OPAE) software development kit (SDK) packages.

Known Issues

This table describes the known issues for the 2023.1 OFS Release targeting Intel Agilex devices.

IDKnown IssuesWorkaroundStatus
15012246661When enabling cable hotplug IP and ANLT, the E-tile recipe resulting from the ANLT initialization flow is over-written by the hotplug initialization flow. If you require a custom ANLT recipe, then you cannot use hotplug at this time.Disable hotplug by writing 1 to index-0 of HSSI Hotplug Debug Control Register (offset 0x600B4) followed by a port level reset or analog reset. Fixed in a future version of OFS FIM for Intel Agilex devices.
14017669281The version of cable hotplug IP in this release supports the VSR (very short route) recipes only.NoneSupport for the LR (long range) recipes will be available in a future release of the OFS for Intel Agilex devices.
14019349213he_random_long_test and mmio_stress_test generate mmio_timeout_errors.NoneFixed in a future version of OFS.
22018273793When sending greater than 1400 byte packets upstream to the PCIe subsystem, you should disable the protocol checker in the src/top/top.sv file to prevent packet stalls.NoneFixed in a future version of OFS.
14019381876The ofs-f2000x reference design does not have the Ethernet link and status LED logic enabled to work with the Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PLNoneFixed in a future version of OFS.

Important Notes

The following section provides important information about this release:

IDImportant Notes
-When using the PF/VF configuration tool to reconfigure the PF/VF mux, you must keep at least one physical function and one virtual function on PF0. The tool does not support less than one PF and one VF on PF0. All other PFs and VFs can be removed if desired.
Assets 8
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