MPF VC Map
On platforms with multiple physical channels connecting the FPGA to system memory, CCI-P multiplexes these channels into a single logical connection. On some physical channel classes, such as PCIe, it is very difficult to determine that a channel write request has committed to system memory without sacrificing bandwidth or latency. For these channels, CCI-P returns its write response when requests are committed to the channel by the FPGA. The write responses are thus intra-channel order guarantees and not inter-channel order guarantees. Despite the write response, a race remains between two conflicting requests that are mapped to separate physical channels because the commit guarantees only that requests have entered the channel and not that they have committed to system memory. The extremely costly write fence request to the VA channel is the only way to guarantee synchronization of requests to the same address on different physical channels.
The MPF virtual channel mapper avoids inter-channel races without write fences by employing an address-based mapping of requests to channels. MPF VC Map consumes requests from the AFU on channel eVC_VA. The mapper hashes the incoming addresses and maps requests to specific channels, always guaranteeing to map a given address to the same channel. While this sounds trivial it is not on systems with asymmetric system interconnects. Maximum bandwidth will be achieved only when the correct fraction of traffic is sent to each channel. Furthermore, a given channel's maximum bandwidth may vary depending on several factors such as request sizes and the ratio of reads to writes. VC Map dynamically optimizes channel bandwidth by tracking traffic patterns and using a table to choose optimal mapping ratios. When traffic patterns change, VC Map may choose to adjust the mapping ratios.