MPF WRO Write Read Order
The MPF WRO shim enforces temporal order for reads and writes to the same address, ordering reads with respect to writes and writes with other writes. WRO only enforces order for references to the same address. It has no effect on requests to disjoint addresses!
Enforcing order is necessarily costly. FPGA area is consumed by WRO filters and buffers. Conflicting requests must be delayed until earlier requests on which they depend are committed to memory.
A traditional CPU memory subsystem enforces order using a content addressable memory (CAM). With a CAM it is possible to match new requests with conflicting requests already in flight. Unfortunately, the hundreds of comparators required for a CCI-P CAM is unacceptably area-intensive on an FPGA. Instead, WRO employs a hash-based tracker, storing the states of hashed trackers in block RAM. Because of the hashing, false conflicts are possible that unnecessarily delay requests. WRO balances filter size with FPGA area in an effort to reduce the false positive rate low enough that it does not affect memory bandwidth.
WRO is enabled by setting ENFORCE_WR_ORDER when instantiating MPF. In addition, ENABLE_VC_MAP must also be set in order to avoid races between writes on one physical channel followed by reads to the same address on another physical channel. Without VC Map an unacceptably expensive write fence would be required before every such conflict.