Pinned Loading
-
Computer-Architecture
Computer-Architecture PublicThese were the assignments of CSE 620: Advanced Computer Architecture, supervised by Prof. Mohamed Watheq El-Kharashi
Verilog
-
-
-
PI-based-CDR
PI-based-CDR PublicIn Cadence, the CDR is designed entirely in a 65nm CMOS technology, based on A 12.5GHz High-Speed Data Link Berkeley 2018.
-
Phase-Aligner
Phase-Aligner PublicAn automatic phase alignment which the quarter-rate 4:1 MUX adopts to eliminate the timing constraint in the transmitter.
-
4-1-Half-Rate-Multiplexer
4-1-Half-Rate-Multiplexer PublicA serializer consists of two 2:1 MUX stages
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.