Remove component declarations from VHDL source

[Araneidae]

After a quick investigation by @glennchid it looks as if component declarations are not required when instantiating Xilinx IP. As there is no other good reason to use component declaration, and they are present in numerous VHDL files, they should all be removed!

[glennchid]

Unfortunately it looks like it may not be possible to get rid components altogether. In doing development on the PandASync module I removed the component declaration for the MGT IP for the Zynq-7000 target and it built and functioned fine. However for the Zynq U/S+ target it appeared to build okay (at first sight) using direct instantiation of the IP, but the MGT would not come out of reset on the hardware. Looking in more detail at the implementation, there were strange messages regarding port directions which did not make sense, but I can no longer remember the details (but could probably reproduce if necessary).

The main difference I could see between the IPs was that one was generated in VHDL and the other verilog. Unfortunately we have no way of controlling this, and in principle this could change with different versions of the generators. I suspect that we can get away with direction instantiation for IP generated in VHDL, but will have to use component instantiation for verilog (which would be expected if instantiating verilog RTL code). Given that using components is the usual/recommended way instantiate IP I suggest we stick with that.

[Araneidae]

I would say that interfacing to external IP is a reasonable case for using components, but it would be nice to if this were tucked away inside a wrapper. I imagine that Verilog IP will generally benefit from wrapping anyway.