Skip to content
View Penchal9959's full-sized avatar

Block or report Penchal9959

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Penchal9959/README.md

Pinned Loading

  1. DATAPATH-CONTROLPATH DATAPATH-CONTROLPATH Public

    A datapath is a collection of functional units such as arithmetic logic units or multipliers that perform data processing operations, registers, and buses.

    Verilog 1

  2. DUAL-PORT-RAM DUAL-PORT-RAM Public

    Dual-ported RAM (DPRAM) is a type of random-access memory that allows multiple reads or writes to occur at the same time, or nearly the same time, unlike single-ported RAM which allows only one acc…

    Verilog 1

  3. FSM-SEQUENCE-DETECTOR FSM-SEQUENCE-DETECTOR Public

    A sequence detector is a sequential state machine that takes an input string of bits and generates an output 1 whenever the target sequence has been detected.

    Verilog 1