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Extended support of Alveo boards by BSC #150
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Extended support of Alveo boards by BSC #150
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… and update arbiter_noc2
Extension of 100GbE test app for support of Aurora DMA IP. See merge request meep/FPGA_implementations/AlveoU280/meep_openpiton!109
Updated VPU, XBAR, LVRF, ME and SAs See merge request meep/FPGA_implementations/AlveoU280/meep_openpiton!107
Update of 100GbE test app to support ping exchange for Aurora. See merge request meep/FPGA_implementations/AlveoU280/meep_openpiton!115
Making default 100GbE port QSFP0. See merge request meep/FPGA_implementations/AlveoU280/meep_openpiton!117
…n packet = single word.
Update of Eth/Aurora test application. See merge request meep/FPGA_implementations/AlveoU280/meep_openpiton!121
MEEP Shell: adding JTAG interface being disabled to accelerator_def.csv. See merge request meep/FPGA_implementations/AlveoU280/meep_openpiton!122
…erge/openpiton-dev
…into merge/openpiton-dev.
…r_def.csv` from BSCAN based to PCIe based.
++ @Jbalkind |
Thanks Alex! This is great :) There's a lot in here (my browser freezes reading the "files changed" tab) and I'm wondering how we can scale this down to make merging it more manageable. There are also a few things I can see from a quick initial scan that I think we should check over or pare down for the initial merge. Initial comments:
Could we also rewrite the history down to a smaller number of commits? That or I could do a squashed merge when I actually merge the PR into the repo. |
Thanks Jon for the feedback. |
Ok that all sounds good. I think going for a squash at merge time is reasonable so let's assume that we'll do that. Thanks! |
…ts for DDR mem (2 inactive ports are present by default).
Hi @Jbalkind , sorry for a delay. Some update is here: now Ariane patching is done through |
Here is a suggested support of 3 types of AMD Alveo boards: U55C, U280, U250. It is based on embedded meep_shell which includes QDMA based PCIe inteface, 2 kinds of supported DRAM: DDR and HBM, support of multi-MC (Memory Controllers) connection to HBM utilizing free NOC ports of edge tiles. Apart of this the contribution includes modified NOC-AXI4 bridge, 100GbE solution based on Ultrascale+ CMAC hard-macro+QSFP and AXI-DMA+SRAM, BSCAN based small JTAG shell. Support of Alveo boards is provided as independent of Vivado versions. The last checked Vivado version is 2024.1. The bitstream built in different configurations and utilizing all above is Linux bootable.