Small ASM tests for the RISC-V Physical Memory Protection unit, on top of a Verilator emulator.
To build and run the different tests, a RISC-V toolchain installation is needed as well as a core Verilator emulator (Rocket or CVA6 for example):
export RISCV=/path/to/the/toolchain
export EMULATOR=/path/to/compiled/emulator
You can then build the elf
/dump
/core log / vcd
using:
make bin/<test_name>.elf|dump|corelog|vcd
For mmode_tor2
for example:
make bin/mmode_tor2.corelog
Note: Intermediate files are deleted by make as the makefile does not explicitely state them..... I'd rather not expand the makefile and specify the needed intermediate file through make directly if needed, (e.g.
make bin/mmode_tor2.elf
to access theelf
file, etc.). If you want to keep all intermediate files, I found that replacing%
in the following snippets with the actual name will keep them (needs to be duplicated for each new test though 🥱)
bin/%.elf: $(COMS_O) $(bin_dir)/%.o $(RISCV_GCC) $(RISCV_LINK_OPTS) $^ -o $@
The tests workflow is the following:
main
: that stores thedata_region0
address ins2
anddata_region1
ins3
pmp_setup
: that fills thepmpaddri
andpmpcfgi
registers in M-modetest_start
: that tries to access memory (either in U-mode or M-mode)
The different data_regioni
contain the same data.bin
, a 256-word iteration (0x00000000, 0x00000001, ...). They are 0x100
aligned and usually end up at 0x80000d00
, 0x0x80000e00
, etc. (this can be checked in the dumps!)