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Saving circuit.layout after transpiling #2736

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merged 12 commits into from
Jul 4, 2019
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@1ucian0 1ucian0 commented Jul 3, 2019

This is an alternative to PR #2721 (and fixes #2584).

This change "saves" the layout into a circuit property after transpiling.

I would like to mentioning that, in the light of #2579, drawing the circuit during debugging will not include the layout using this approach.

lia-approves pushed a commit to edasgupta/qiskit-terra that referenced this pull request Jul 30, 2019
* from unittest.mock import patch

* .

* alternative to 2721

* test

* remove subtest
@1ucian0 1ucian0 deleted the 2721 branch August 6, 2019 20:05
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Need Consistent Layout Representations During Transpile
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