P(32,0)

[MortezaYou]

Hi,
This issue is resolved.
Thank you so much . . .

[RaulMurillo]

Just to know, was there any problem with the VHDL design?

[MortezaYou]

Unfortunately, the problem still exists, when we use P(32,0), the multiplier has a large reduction in power compared to P(32,2). Do you agree with this?

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On Thu, Apr 6, 2023, 10:40 AM Raul Murillo Montero ***@***.***> wrote: Just to know, was there any problem with the VHDL design? — Reply to this email directly, view it on GitHub <#5 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AD4MZRJ47Z3B62V2S5VGFQ3W7ZT4RANCNFSM6AAAAAAWPX6ABY> . You are receiving this because you modified the open/close state.Message ID: ***@***.***>

[RaulMurillo]

Sorry for the delay.
How are you getting the power report?
I am using the same ASIC synthesis tool and configuration I used in the original paper to obtain the results shown in the /figsdirectory (Synopsys DC, with 45 nm TSMC library).
The area, delay and power results follow the expected trend: the P(32,0) multiplier requires more resources compared to P(32,2) unit. This is because in the 0-exponent case the fraction field will be 2 bits larger, and thus the hardware multiplier (which is the most power-hungry submodule) will be larger as well.

[MortezaYou]

Thank you,
So I need to check my results more.