GitHub - Regis111/dice_on_fpga: Vhdl and SystemVerilog code which executed accomplishes simple task of function rand() for numbers from 1 to 6

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Vhdl and SystemVerilog code which executed accomplishes simple task of function rand() for numbers from 1 to 6

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Name		Name	Last commit message	Last commit date
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vhdl		vhdl
verilog.sv		verilog.sv

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Vhdl and SystemVerilog code which executed accomplishes simple task of function rand() for numbers from 1 to 6

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