ARM: dts: stm32: add delay block support and higher sd-uhs speeds on stm32mp157

To reach SDR50, DDRR50 and SDR104 speed on SDMMC, a delay block is
required. The addresses of the delay blocks of each SDMMC instance
is added in SoC DT file.
The sd-uhs-sdr50, sd-uhs-ddr50 and sd-uhs-sdr104 properties are added
for STM32MP1 ED1/EV1 boards.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I322e095ad0092d4336a45274fd24aa9dac65fddf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/148130
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Reviewed-by: Alexandre TORGUE <alexandre.torgue@st.com>

Author: Yann-lms

arch/arm/boot/dts/stm32mp157c-ed1.dts

@@ -300,6 +300,9 @@
 	vqmmc-supply = <&sd_switch>;
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
 	status = "okay";
 };
 

arch/arm/boot/dts/stm32mp157c.dtsi

@@ -1105,7 +1105,7 @@
 		sdmmc3: sdmmc@48004000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x10153180>;
-			reg = <0x48004000 0x400>;
+			reg = <0x48004000 0x400>, <0x48005000 0x400>;
 			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
 			clocks = <&rcc SDMMC3_K>;
@@ -1453,7 +1453,7 @@
 		sdmmc1: sdmmc@58005000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x10153180>;
-			reg = <0x58005000 0x1000>;
+			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
 			clocks = <&rcc SDMMC1_K>;
@@ -1468,7 +1468,7 @@
 		sdmmc2: sdmmc@58007000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x10153180>;
-			reg = <0x58007000 0x1000>;
+			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
 			clocks = <&rcc SDMMC2_K>;