Interface BSCAN2 with VexRiscv's JTAG

[ztachip]

Hi
I am trying to use Xilinx BSCAN2 for JTAG debugging but I try to instantiate BSCAN2 outside of VexRiscv and just route the JTAG signals to VexRiscv (based on Briey.scala design with JTAG).
The reason is that I try to keep my project easy to port between different FPGA by isolating the portable HDL codes from the components that are specific to FPGA silicon. That's why I look for way to do JTAG over BSAN2 but without referencing VexRiscv's jtagCtrl.fromXilinxBscane2 function since I would like to keep the soft-CPU to be the portable component.
But so far openocd fails to communicate with VexRiscv this way.
Should this work or there are some logic to apply to BSAN2's signals before they can be routed to VexRiscv.
Thanks

[Dolu1990]

Hi

Have you seen this doc ? :
https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag
Which bscane2 id did you used ?

[ztachip]

Hi I am working on a project that I try to keep it portable between different FPGA as much as possible. Yes, I did try the method described in the doc and it works well. But what I try to do is to instantiate BSCAN2 outside of VexRiscv. This way VexRiscv remains portable between different FPGA since it will just reference standard JTAG signal like TCLK,TDO,TDI,,, Wondering if you can share information how you convert BSCAN2 to JTAG signals. Thanks

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________________________________ From: Dolu1990 ***@***.***> Sent: October 11, 2023 7:23 AM To: SpinalHDL/VexRiscv ***@***.***> Cc: ztachip ***@***.***>; Author ***@***.***> Subject: Re: [SpinalHDL/VexRiscv] Interface BSCAN2 with VexRiscv's JTAG (Issue #370) Hi Have you seen this doc ? : https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag Which bscane2 id did you used ? — Reply to this email directly, view it on GitHub<#370 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/ACSDUFU2AZLYQ3DBRADGFILX6Z6TXANCNFSM6AAAAAA5ZCYLZA>. You are receiving this because you authored the thread.Message ID: ***@***.***>

[Dolu1990]

Ahh i would say you would have two ways,
Either you expose the jtag instruction interface (bscane like) which can be then bridged to something else. And in the case you want to bridge it from a true 4 pins jtag, you just need to create a little jtag tap which "behave like the bscane2"

Something like :

       val jtag = slave(new Jtag())
        val jtagClockDomain = ClockDomain(jtag.tck) on new Area
          val tap = new JtagTap(jtag, 6)
          val idcodeArea = tap.idcode(B(p.tapId, 32 bits))(5)
          val wrapper = tap.map(debug.jtagInstruction, instructionId = 8)
        }
        

Either you expose the native vex debug interface, which is a small memory bus, and then you provide the bridge from what ever -> to it.