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Finite-State Machine Design of a Simple Car Security Alarm on FPGA
VHDL
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FSM_CarAlarm.jpg
FSM_CarAlarm.vhd
FSM_CarAlarm_modelsim.jpg
FSM_CarAlarm_tb.vhd
README.md

README.md

FSM_CarAlarm

Finite-State Machine Design of a Simple Car Security Alarm on FPGA

Information

This is a VHDL project for DSD-I1* a Cyclone IV FPGA made in Quartus 18.1 and is based in the example of the book Pedroni 2008.

Diagram:
Diagram

Behavioral VHDL code: FSM_CarAlarm.vhd
Testbench VHDL code: FSM_CarAlarm_tb.vhd

Modelsim:
FPGA

*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education DOI:10.1109/DSD.2019.00032

Licence

Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) stavros@ubinet.gr. It is free software, and may be redistributed under the terms of the GNU Licence.

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