PhD researcher, Member of the Electronic Circuits, Systems and Applications (@ECSAlab) Laboratory
Highlights
- Pro
Pinned Loading
-
4bitCounterParLoad
4bitCounterParLoad PublicA 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder
VHDL 1
-
-
FSM_CarAlarm
FSM_CarAlarm PublicFinite-State Machine Design of a Simple Car Security Alarm on FPGA
VHDL 2
-
CastaliaGCF
CastaliaGCF PublicRouting Algorithm for Mobile Agent (MA) based Wireless Sensor Network (WSN) on Castalia Simulator
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.