FPGA Interchange Global Clock Routing

[gatecat]

Prerequisites:

• wire types, as being discussed in Add Wire types and categories chipsalliance/fpga-interchange-schema#31
• specification for more complex rules, UltraScale clock routing chipsalliance/fpga-interchange-schema#34

Global clock routing is likely to be based on a BFS, at least to start with, primarily from the sink back to the root but following certain wire type constraints and aiming to maximise shared routing along the way. This approach has worked well for previous devices - see Nexus example:

https://github.com/YosysHQ/nextpnr/blob/3fd1ee7757356660c7f440705553d345837eaed5/nexus/global.cc#L45-L137

Similarly, such approach could also be used to determine placements for global buffers that maximise use of dedicated resources automatically, similar to https://github.com/YosysHQ/nextpnr/blob/3fd1ee7757356660c7f440705553d345837eaed5/nexus/pack.cc#L674-L797. For cases where this doesn't work; manual associations as described in #263 will be needed.

Finally, UltraScale clock routing will need some logic to find the clock root and route to/from it.