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Routing fails without explicitly inserted BUFG on clock #570
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Because I am not sure what are the relevant inputs, I have put the whole project on Github at https://github.com/gergoerdi/vtr-verilog-to-routing-issue-570. It is basically a subdir from |
The version of Symbiflow I am using is from https://github.com/SymbiFlow/symbiflow-examples version 07a6353627e0b6083728d1022ce30f9093d4c2de |
Hi @gergoerdi, inserting a BUFG at the MMCM_25 u_MMCM_25
(.CLKIN_100MHZ(CLK100MHZ),
.CLKOUT_25MHZ(CLK_25MHZ),
.LOCKED(CLK_LOCKED)
);
wire CLK_25MHZ_BUFG;
BUFG BUFG(.I(CLK_25MHZ), .O(CLK_25MHZ_BUFG));
topEntity u_topEntity
(.CLK_25MHZ(CLK_25MHZ_BUFG),
...
|
Indeed, adding a Does this make this a PEBKAC and I should close the ticket, or is it still a valid issue that it didn't work without the |
I think that we may leave this open and close it until whichever one of the following is done:
|
I am trying to synthesize a very simple circuit, targeting
xc7a50tcsg324-1
. I can take the same input and synthesize all the way to a bitfile with Vivado.VPR fails with the following lengthy output:
The text was updated successfully, but these errors were encountered: