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Removing "if(1)" Conditions #50

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leolitenstorrent opened this issue Jun 22, 2023 · 2 comments
Closed

Removing "if(1)" Conditions #50

leolitenstorrent opened this issue Jun 22, 2023 · 2 comments
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feature request New feature or request

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@leolitenstorrent
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leolitenstorrent commented Jun 22, 2023

Hello Alex,

I noticed that for single pulse registers, PeakRDL-regblock is generating if(1) conditions for resetting the registers back to 0, such as in the code below.

            ....
            load_next_c = '1;
        end else if(1) begin // singlepulse clears back to 0
            next_c = '0;
            load_next_c = '1;
        end

May I request that the if(1) conditions be omitted for singlepulse registers (and other components/registers), because it generates warning messages and has the possibility to cause synthesizers to generate extra logic?

Thank you!

@amykyta3 amykyta3 self-assigned this Jun 24, 2023
@amykyta3 amykyta3 added the feature request New feature or request label Jun 24, 2023
@amykyta3
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Agree this should be cleaned up.

The generator code even has a TODO comment for this exact thing. Thanks for the reminder 😄!

@amykyta3
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Will be fixed in next release

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