GitHub - TCLaurentiu/cpu: RISC CPU

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Asamblor		Asamblor
Verilog		Verilog
FIC Tests.pdf		FIC Tests.pdf
Proiect FIC.rar		Proiect FIC.rar
input.txt		input.txt
requirements.md		requirements.md
schema.PDF		schema.PDF
schema.SVG		schema.SVG
test.asm		test.asm
test.txt		test.txt
testing_script.sh		testing_script.sh