Constraining OpenROAD flow for ensuring outputs are from flip-flops

[ishwars1618]

Hello,
I am trying to use OpenROAD flow to generate the layout for a simple single-stage feed-forward sequential circuit expressed in structural Verilog. The primary input signals of the circuit feed to a set of D flip-flops, followed by combinational logic, and the outputs of the combinational logic feed to another set of D flip-flops. The outputs of these D flip-flops are the outputs of my circuit. When I run the OpenROAD flow (with asap7), both the synthesis output Verilog and the final Verilog have inverters that provide the circuit outputs rather than D flip-flops. How can I constrain the flow such that the circuit outputs are from D flip-flops (as it was in the input Verilog)? Thanks.

[maliberty]

If they are there in the yosys output that that is where the issue and they are just passing through OR. Can you provide a test case?

[ishwars1618]

Yes, the inverters are there in the yosys output too right after synthesis. Attached are the files for the test case (modified version of ISCAS c17). I added a .txt extension to the input Verilog file, config.mk and constraint.sdc files to be able to upload them.

c17s1.v.txt
config.mk.txt
constraint.sdc.txt

Thanks.

[maliberty]

if you look at DFFLQNx1_ASAP7_75t_R you'll see it is inverting so the inverter is required to match your dff which is non-inverting.

[ishwars1618]

Yes, but couldn't Yosys have chosen either a non-inverting D flip flop from ASAP7, or alternatively pushed the final inverter to the input of the inverting D flip-flop? I wanted to enforce that all outputs (and inputs) are flopped. Current result contains combinational logic (inverters) dangling after the flops. Should I contact Yosys support in OpenROAD, and if so, who would it be? Thanks for your feedback.

[maliberty]

It would be a yosys enhancement

[rovinski]

Assuming that the non-inverting DFFs are compatible with yosys and you don't want to use them at all, I believe you can simply add that cell to the DONT_USE list.