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23 Open 213 Closed
23 Open 213 Closed
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Issues list

Add a helper function to encode 1-hot to binary
#455 opened Oct 16, 2024 by vaaniarora
2
Improve block visualization
#451 opened Jun 1, 2024 by fdxmw
Improve handling of signed numbers
#450 opened Jun 1, 2024 by fdxmw
Improve notebook support
#449 opened May 31, 2024 by fdxmw
Add wire_struct and wire_matrix examples
#448 opened May 31, 2024 by fdxmw
Optimize is currently missing the elimination of "double not" beginner friendly A good target for undergrads to contribute to PyRTL enhancement Proposed feature requests and improvements
#447 opened May 27, 2024 by timsherwood
Right shift operation semantics difference fix before version 1.0
#443 opened Apr 27, 2024 by timsherwood
Wires used but never driven
#422 opened Aug 6, 2022 by JulianKemmerer
6
"toplevel" in verilog output is hardcoded beginner friendly A good target for undergrads to contribute to PyRTL enhancement Proposed feature requests and improvements
#420 opened Jun 13, 2022 by bjourne
Add bitmasked write to memories
#418 opened May 21, 2022 by timsherwood
1
fixed point enhancement Proposed feature requests and improvements
#417 opened May 20, 2022 by timsherwood
1
Add unit tests for different types of possible flip-flops importable as BLIF
#414 opened Feb 12, 2022 by mdko
1
Find better way to handle special WireVector subclasses like _MemIndexed confusing or uncaught error PyRTL error messages not sufficient for situation
#406 opened Sep 23, 2021 by mdko
Add automatic testing of Jupyter notebook files testing For issues related to unit tests and continuous integration.
#376 opened Jun 4, 2021 by mdko
1
Documentation missing interface for Block beginner friendly A good target for undergrads to contribute to PyRTL
#375 opened Jun 1, 2021 by timsherwood
Implement wrap_around in the barrel_shifter fix before version 1.0
#355 opened May 4, 2021 by mdko
Improve CompiledSimulation Iteration over Memory enhancement Proposed feature requests and improvements
#320 opened Feb 24, 2021 by mdko
@mdko
Make FastSimulation faster by combining it with Simulation
#265 opened Aug 29, 2019 by drholmie
Using output as a source (rather than a dest) throw internal error instead of user error beginner friendly A good target for undergrads to contribute to PyRTL confusing or uncaught error PyRTL error messages not sufficient for situation
#263 opened Jul 2, 2019 by timsherwood
ipynb examples - Example #4: use set_debug_mode() to provide more information
#245 opened Oct 15, 2018 by kmahorker
Add examples uses to the documentation beginner friendly A good target for undergrads to contribute to PyRTL enhancement Proposed feature requests and improvements fix before version 1.0
#236 opened May 31, 2018 by timsherwood
Controlling hardware simulation: Python test benches?
#226 opened Dec 19, 2016 by abe-k
11
Synchronous Reset for FPGA enhancement Proposed feature requests and improvements
#162 opened Jun 30, 2016 by jemcmahan13
1
ProTip! Updated in the last three days: updated:>2024-11-05.