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Support upstream ariane #2

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Support upstream ariane #2

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bad8025
Changes for upstream ariane in openpiton
Jbalkind Apr 5, 2022
205bef5
Bumping ariane pointer
Jbalkind May 2, 2022
af64311
Stop checking invalid accesses by default in packet filter
Jbalkind May 2, 2022
54c93f0
Bump ariane pointer to fix breaking changes
Jbalkind Aug 27, 2022
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2 changes: 1 addition & 1 deletion piton/design/chip/tile/ariane
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Submodule ariane updated from cbbcf3 to 802e75
4 changes: 2 additions & 2 deletions piton/design/chip/tile/rtl/tile.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,8 @@ if PITON_ARIANE:
sysFreq = int(os.environ['CONFIG_SYS_FREQ'])

timeStamp = time.strftime("%b %d %Y %H:%M:%S", time.localtime())
gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['ARIANE_ROOT']+"/openpiton/bootrom/", timeStamp)
get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['ARIANE_ROOT']+"/openpiton/bootrom/", timeStamp)
gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['ARIANE_ROOT']+"/corev_apu/openpiton/bootrom/", timeStamp)
get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['ARIANE_ROOT']+"/corev_apu/openpiton/bootrom/", timeStamp)
%>

module tile #(
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11 changes: 1 addition & 10 deletions piton/design/chipset/rtl/packet_filter.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -325,14 +325,6 @@ for i in range(1, len(devices)):

outputstr = """
else begin
`ifdef PITON_FPGA_SYNTH
// route everything else to the memory when uart_boot_en is asserted
if (%s (uart_boot_en)) begin
readdressed_flit0[`MSG_DST_X] = `NOC_X_WIDTH'h%x;
end else begin
invalid_access = 1'b1;
end
`else // PITON_FPGA_SYNTH
`ifdef MONITOR_INVALID_ACCESSES
// route everything else to the memory when uart_boot_en is asserted
if (%s (uart_boot_en)) begin
Expand All @@ -344,9 +336,8 @@ outputstr = """
// route everything else to the memory in simulation
readdressed_flit0[`MSG_DST_X] = `NOC_X_WIDTH'h%x;
`endif // MONITOR_INVALID_ACCESSES
`endif // PITON_FPGA_SYNTH
end
""" % (mem_addr_range, mem_port, mem_addr_range, mem_port, mem_port)
""" % (mem_addr_range, mem_port, mem_port)
print(outputstr)
%>
end
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23 changes: 3 additions & 20 deletions piton/tools/bin/riscvlib.py
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Original file line number Diff line number Diff line change
Expand Up @@ -142,11 +142,9 @@ def gen_riscv_dts(devices, nCpus, cpuFreq, timeBaseFreq, periphFreq, dtsPath, ti
#size-cells = <2>;
compatible = "eth,ariane-bare-dev";
model = "eth,ariane-bare";
// TODO: interrupt-based UART is currently very slow
// with this configuration. this needs to be fixed.
// chosen {
// stdout-path = "/soc/uart@%08x:115200";
// };
chosen {
stdout-path = "/soc/uart@%08x:115200";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
Expand Down Expand Up @@ -244,21 +242,6 @@ def gen_riscv_dts(devices, nCpus, cpuFreq, timeBaseFreq, periphFreq, dtsPath, ti
riscv,ndev = <%d>;
};
''' % (_reg_fmt(addrBase, addrLen, 2, 2), numIrqs)
# DTM
if devices[i]["name"] == "ariane_debug":
addrBase = devices[i]["base"]
addrLen = devices[i]["length"]
tmpStr += '''
debug-controller@%08x {
compatible = "riscv,debug-013";
interrupts-extended = <''' % (addrBase)
for k in range(nCpus):
tmpStr += "&CPU%d_intc 65535 " % (k)
tmpStr += '''>;
reg = <%s>;
reg-names = "control";
};
''' % (_reg_fmt(addrBase, addrLen, 2, 2))
# UART
if devices[i]["name"] == "uart":
addrBase = devices[i]["base"]
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10 changes: 10 additions & 0 deletions piton/tools/src/proto/common/pyhp_preprocess.tcl
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Expand Up @@ -37,8 +37,18 @@ proc pyhp_preprocess {RTL_IMPL_FILES} {
append GEN_RTL_IMPL_FILE "tmp."
append GEN_RTL_IMPL_FILE [string index ${RTL_IMPL_FILE} [expr ${RTL_IMPL_FILENAME_LEN} - 1]]

# credit goes to https://github.com/PrincetonUniversity/openpiton/issues/50
# and https://www.xilinx.com/support/answers/72570.html
set tmp_PYTHONPATH $::env(PYTHONPATH)
set tmp_PYTHONHOME $::env(PYTHONHOME)
unset ::env(PYTHONPATH)
unset ::env(PYTHONHOME)

# Run PyHP
exec pyhp.py ${PYV_IMPL_FILE} > ${GEN_RTL_IMPL_FILE}

set ::env(PYTHONPATH) $tmp_PYTHONPATH
set ::env(PYTHONHOME) $tmp_PYTHONHOME

# Append to new source file list
set GEN_RTL_IMPL_FILES "${GEN_RTL_IMPL_FILES} ${GEN_RTL_IMPL_FILE}"
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274 changes: 144 additions & 130 deletions piton/tools/src/proto/common/rtl_setup.tcl
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16 changes: 8 additions & 8 deletions piton/tools/src/proto/common/setup.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -124,18 +124,18 @@ if {[info exists ::env(PITON_ARIANE)]} {

# credit goes to https://github.com/PrincetonUniversity/openpiton/issues/50
# and https://www.xilinx.com/support/answers/72570.html
set tmp_PYTHONPATH $env(PYTHONPATH)
set tmp_PYTHONHOME $env(PYTHONHOME)
unset ::env(PYTHONPATH)
set tmp_PYTHONPATH $::env(PYTHONPATH)
set tmp_PYTHONHOME $::env(PYTHONHOME)
unset ::env(PYTHONPATH)
unset ::env(PYTHONHOME)

set TMP [pwd]
cd $::env(ARIANE_ROOT)/openpiton/bootrom/baremetal
cd $::env(ARIANE_ROOT)/corev_apu/openpiton/bootrom/baremetal
# Note: dd dumps info to stderr that we do not want to interpret
# otherwise this command fails...
exec make clean 2> /dev/null
exec make all 2> /dev/null
cd $::env(ARIANE_ROOT)/openpiton/bootrom/linux
cd $::env(ARIANE_ROOT)/corev_apu/openpiton/bootrom/linux
# Note: dd dumps info to stderr that we do not want to interpret
# otherwise this command fails...
exec make clean 2> /dev/null
Expand All @@ -145,12 +145,12 @@ if {[info exists ::env(PITON_ARIANE)]} {
set NUM_TARGETS [expr 2*$::env(PITON_NUM_TILES)]
set NUM_SOURCES 2
puts "INFO: generating PLIC for Ariane ($NUM_TARGETS targets, $NUM_SOURCES sources)..."
cd $::env(ARIANE_ROOT)/src/rv_plic/rtl
cd $::env(ARIANE_ROOT)/corev_apu/rv_plic/rtl
exec ./gen_plic_addrmap.py -t $NUM_TARGETS -s $NUM_SOURCES > plic_regmap.sv

cd $TMP
puts "INFO: done"
set ::env(PYTHONPATH) $tmp_PYTHONPATH
set ::env(PYTHONHOME) $tmp_PYTHONHOME
set ::env(PYTHONPATH) $tmp_PYTHONPATH
set ::env(PYTHONHOME) $tmp_PYTHONHOME
}

6 changes: 3 additions & 3 deletions piton/tools/src/sims/sims,2.0
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Original file line number Diff line number Diff line change
Expand Up @@ -1276,17 +1276,17 @@ sub pre_build

if($opt{ariane}) {
print "compiling DTS and bootroms for Ariane...\n";
!system("cd $ENV{ARIANE_ROOT}/openpiton/bootrom/baremetal && make clean && make all && cd - > /dev/null") or
!system("cd $ENV{ARIANE_ROOT}/corev_apu/openpiton/bootrom/baremetal && make clean && make all && cd - > /dev/null") or
die (" Error compiling DTS for ariane.");
!system("cd $ENV{ARIANE_ROOT}/openpiton/bootrom/linux && make clean && make all MAX_HARTS=$ENV{PITON_NUM_TILES} && cd - > /dev/null") or
!system("cd $ENV{ARIANE_ROOT}/corev_apu/openpiton/bootrom/linux && make clean && make all MAX_HARTS=$ENV{PITON_NUM_TILES} && cd - > /dev/null") or
die (" Error compiling DTS for ariane.");
print "done\n";
# currently we have two sources (hardcoded in chipset_impl): UART and Ethernet
my $num_sources = 2;
# 2 targets per core (M/S mode)
my $num_targets = 2 * $ENV{PITON_NUM_TILES};
print "generating PLIC for Ariane with $num_targets targets and $num_sources sources...\n";
!system("cd $ENV{ARIANE_ROOT}/src/rv_plic/rtl && ./gen_plic_addrmap.py -t $num_targets -s $num_sources > plic_regmap.sv") or
!system("cd $ENV{ARIANE_ROOT}/corev_apu/rv_plic/rtl && ./gen_plic_addrmap.py -t $num_targets -s $num_sources > plic_regmap.sv") or
die (" Error generating PLIC for Ariane.");
print "done\n";
}
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1 change: 0 additions & 1 deletion piton/verif/diag/assembly/include/riscv/ariane/encoding.h
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