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Added doc-strings.
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pyVHDLModel/DesignUnit.py

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@@ -58,6 +58,16 @@
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@export
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class Reference(ModelEntity):
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"""
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A base-class for all references.
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.. seealso::
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* :class:`~pyVHDLModel.DesignUnit.LibraryClause`
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* :class:`~pyVHDLModel.DesignUnit.UseClause`
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* :class:`~pyVHDLModel.DesignUnit.ContextReference`
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"""
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_symbols: List[Symbol]
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def __init__(self, symbols: Iterable[Symbol]):
@@ -72,18 +82,48 @@ def Symbols(self) -> List[Symbol]:
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@export
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class LibraryClause(Reference):
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pass
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"""
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Represents a library clause.
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.. admonition:: Example
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.. code-block:: VHDL
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library ieee;
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"""
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@property
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def Symbols(self) -> List[LibraryReferenceSymbol]:
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return self._symbols
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@export
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class UseClause(Reference):
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pass
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"""
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Represents a use clause.
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.. admonition:: Example
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.. code-block:: VHDL
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use ieee.numeric_std.all;
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"""
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@export
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class ContextReference(Reference):
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# TODO: rename to ContextClause?
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pass
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"""
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Represents a context reference.
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.. hint:: It's called *context reference* not *context clause* by the LRM.
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.. admonition:: Example
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.. code-block:: VHDL
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context ieee.ieee_std_context;
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"""
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@export
@@ -93,7 +133,23 @@ class DesignUnitWithContextMixin: # (metaclass=ExtendedType, useSlots=True):
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@export
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class DesignUnit(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
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"""A ``DesignUnit`` is a base-class for all design units."""
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"""
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A base-class for all design units.
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.. seealso::
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* :class:`Primary design units <pyVHDLModel.DesignUnit.PrimaryUnit>`
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* :class:`~pyVHDLModel.DesignUnit.Context`
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* :class:`~pyVHDLModel.DesignUnit.Entity`
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* :class:`~pyVHDLModel.DesignUnit.Package`
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* :class:`~pyVHDLModel.DesignUnit.Configuration`
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* :class:`Secondary design units <pyVHDLModel.DesignUnit.SecondaryUnit>`
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* :class:`~pyVHDLModel.DesignUnit.Architecture`
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* :class:`~pyVHDLModel.DesignUnit.PackageBody`
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"""
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_library: 'Library' #: The VHDL library, the design unit was analyzed into.
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@@ -226,12 +282,28 @@ def HierarchyVertex(self) -> Vertex:
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@export
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class PrimaryUnit(DesignUnit):
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"""A ``PrimaryUnit`` is a base-class for all primary units."""
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"""
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A base-class for all primary design units.
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.. seealso::
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* :class:`~pyVHDLModel.DesignUnit.Context`
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* :class:`~pyVHDLModel.DesignUnit.Entity`
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* :class:`~pyVHDLModel.DesignUnit.Package`
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* :class:`~pyVHDLModel.DesignUnit.Configuration`
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"""
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@export
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class SecondaryUnit(DesignUnit):
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"""A ``SecondaryUnit`` is a base-class for all secondary units."""
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"""
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A base-class for all secondary design units.
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.. seealso::
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* :class:`~pyVHDLModel.DesignUnit.Architecture`
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* :class:`~pyVHDLModel.DesignUnit.PackageBody`
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"""
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@export

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