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Pins are blocked for P&R in generated LEF file #45

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Fatsie opened this issue May 23, 2019 · 4 comments
Closed

Pins are blocked for P&R in generated LEF file #45

Fatsie opened this issue May 23, 2019 · 4 comments

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@Fatsie
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Fatsie commented May 23, 2019

I generated a 1024x8 SRAM block with the scn4m_subm technology. When looking at the LEF files the (input) pins don't seem to be accessible for P&R.
The flip-flops have an OBS on metal1 and metal2 and on metal3 and metal4 the GND/VDD grid is generated.
My design was just test chip with an OpenRAM block, I circumvented the problem by manual connecting the pins out of the block.

@mguthaus
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mguthaus commented May 23, 2019 via email

@Fatsie
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Fatsie commented May 23, 2019

I am using head: 76e2ab8
config:

word_size = 8
num_words = 1024

tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [ 3.3 ]
temperatures = [ 25 ]

output_path = output_name = "SRAM{}x{}".format(num_words, word_size)

route_supplies = True

drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"

@mguthaus
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Sorry for the delay. We are aware and see this problem. There are two fixes that will be available soon to resolve this:

  1. The pins will be brought to M3 on the perimeter.
  2. There is a mistake in generating blockages of the leaf cells (6T, sense amp, DFF). It simply blocks all metal1 and metal2, instead of the detailed blockages in the leaf GDS.

@mguthaus
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mguthaus commented Jul 5, 2019

This is fixed in an upcoming release. Instead of blocking all metal1 and metal2 in the leaf cells, we provide detailed blockages instead.

@mguthaus mguthaus closed this as completed Jul 5, 2019
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