Sense Amplifier enable signal

[robin-tukl]

During my work with the openram layout, I encountered a strange behaviour of the Sense Amplifier enable signal. For me, it looks like the enable signal is only active during the writes (S_en = web and (not csb) and (not clk) ). That means that the output voltage is not stable when you try to read from the SRAM. Is it possible that there is a mistake in the control logic?

[mguthaus]

Please look at the dev branch as we restructured the control logic to be more robust to race conditions and to use replica bitline timing that is part of the main array. This hasn't been pushed to master yet. In the new branch however, we also only activate on reads with the intent that you aren't reading while you write. However, we intended to have a "feed through" write which is not this behavior. I need to look at the timing and see if this would cause any other issues. It might be just a one line fix (to use csb instead of web). Matt

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On Fri, Sep 6, 2019, 02:02 robin-tukl ***@***.***> wrote: During my work with the openram layout, I encountered a strange behaviour of the Sense Amplifier enable signal. For me, it looks like the enable signal is only active during the writes (S_en = web and (not csb) and (not clk) ). That means that the output voltage is not stable when you try to read from the SRAM. Is it possible that there is a mistake in the control logic? — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#51?email_source=notifications&email_token=AC67SL74FZ6N26V647D3HRLQIIMAZA5CNFSM4IUGWBTKYY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4HJYB7IA>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AC67SL2ZQMVV2JF747PH5YDQIIMAZANCNFSM4IUGWBTA> .

[mguthaus]

I'm working on this fix, but it may take a while (travelling international very soon). It turns out our unit test was not checking feed through writes that were read in the same cycle, so this was not tested in our functional simulations. On Fri, Sep 6, 2019 at 6:01 AM Matt Guthaus <notifications@github.com> wrote:

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Please look at the dev branch as we restructured the control logic to be more robust to race conditions and to use replica bitline timing that is part of the main array. This hasn't been pushed to master yet. In the new branch however, we also only activate on reads with the intent that you aren't reading while you write. However, we intended to have a "feed through" write which is not this behavior. I need to look at the timing and see if this would cause any other issues. It might be just a one line fix (to use csb instead of web). Matt On Fri, Sep 6, 2019, 02:02 robin-tukl ***@***.***> wrote: > During my work with the openram layout, I encountered a strange behaviour > of the Sense Amplifier enable signal. For me, it looks like the enable > signal is only active during the writes (S_en = web and (not csb) and (not > clk) ). That means that the output voltage is not stable when you try to > read from the SRAM. Is it possible that there is a mistake in the control > logic? > > — > You are receiving this because you are subscribed to this thread. > Reply to this email directly, view it on GitHub > < #51?email_source=notifications&email_token=AC67SL74FZ6N26V647D3HRLQIIMAZA5CNFSM4IUGWBTKYY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4HJYB7IA >, > or mute the thread > < https://github.com/notifications/unsubscribe-auth/AC67SL2ZQMVV2JF747PH5YDQIIMAZANCNFSM4IUGWBTA > > . > — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#51?email_source=notifications&email_token=AC67SL7DIMSZBUVXHRJYWPDQIJIAZA5CNFSM4IUGWBTKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOD6CYSMA#issuecomment-528845104>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AC67SL4M7CPLQMMNU35EVX3QIJIAZANCNFSM4IUGWBTA> .

-- Matthew Guthaus Associate Dean of Graduate Studies Professor, Computer Science & Engineering Baskin School of Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

[mguthaus]

This logic is from an old version, but it was actually correct at the time. web is active low, so a read would have it be 1 and s_en would be enabled (1). Please update to get improved timing of control logic -- there were some other bugs that are fixed in the dev branch. I was confusing your question with details about writing and reading at the same time which is another issue and behaves as expected. Hope that helps.

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On Sat, Sep 7, 2019, 03:18 Matt Guthaus ***@***.***> wrote: I'm working on this fix, but it may take a while (travelling international very soon). It turns out our unit test was not checking feed through writes that were read in the same cycle, so this was not tested in our functional simulations. On Fri, Sep 6, 2019 at 6:01 AM Matt Guthaus ***@***.***> wrote: > Please look at the dev branch as we restructured the control logic to be > more robust to race conditions and to use replica bitline timing that is > part of the main array. This hasn't been pushed to master yet. > > In the new branch however, we also only activate on reads with the intent > that you aren't reading while you write. However, we intended to have a > "feed through" write which is not this behavior. I need to look at the > timing and see if this would cause any other issues. It might be just a one > line fix (to use csb instead of web). > > Matt > > > > On Fri, Sep 6, 2019, 02:02 robin-tukl ***@***.***> wrote: > > > During my work with the openram layout, I encountered a strange behaviour > > of the Sense Amplifier enable signal. For me, it looks like the enable > > signal is only active during the writes (S_en = web and (not csb) and > (not > > clk) ). That means that the output voltage is not stable when you try to > > read from the SRAM. Is it possible that there is a mistake in the control > > logic? > > > > — > > You are receiving this because you are subscribed to this thread. > > Reply to this email directly, view it on GitHub > > < > #51?email_source=notifications&email_token=AC67SL74FZ6N26V647D3HRLQIIMAZA5CNFSM4IUGWBTKYY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4HJYB7IA > >, > > or mute the thread > > < > https://github.com/notifications/unsubscribe-auth/AC67SL2ZQMVV2JF747PH5YDQIIMAZANCNFSM4IUGWBTA > > > > . > > > > — > You are receiving this because you are subscribed to this thread. > Reply to this email directly, view it on GitHub > < #51?email_source=notifications&email_token=AC67SL7DIMSZBUVXHRJYWPDQIJIAZA5CNFSM4IUGWBTKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOD6CYSMA#issuecomment-528845104 >, > or mute the thread > < https://github.com/notifications/unsubscribe-auth/AC67SL4M7CPLQMMNU35EVX3QIJIAZANCNFSM4IUGWBTA > > . > -- Matthew Guthaus Associate Dean of Graduate Studies Professor, Computer Science & Engineering Baskin School of Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#51?email_source=notifications&email_token=AC67SL5BCUW5REXQVR4SODTQIKUIDA5CNFSM4IUGWBTKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOD6DZ4AQ#issuecomment-528981506>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AC67SL5NJZHH6TUFDULMT43QIKUIDANCNFSM4IUGWBTA> .