Some labs based on Zynq: Zybo - XC7Z010clg400-1.
- Describe general FPGA architectures
- Understand the Vivado design flow
- Create and debug HDL designs
- Synthesize and implement HDL designs
- Utilize the available synthesis and implementation reports to analyze a design(utilization, timing, power, etc.)
- Configure FPGAs and verify hardware operation
- Create and apply I/O and timing constraints
- Use the Project Manager to navigate through the design flow
- Identify file sets(HDL,XDC,simulation)
- Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer.
- Describe the high level synthesis flow
- Understand the control and data path extraction
- Describe scheduling and binding phases of the HLS flow
- Identify steps involved in validation and verification flows
- State various directives which can be helpful in improving performance and resource utilization
- Describe how to use OpenCV functions in the Vivado HLS tool
- Perform system-level integration of blocks generated by the Vivado HLS tool
- Rapidly architect an embedded system targeting Zynq, and the AXI4 interface standard, using Vivado and IP Integrator
- Extend the system by adding peripherals
- Add Xilinx provided peripherals from the IP catalog
- Create and add a custom peripheral using IP Integrator
- Create and debug software applications
- Create software applications in the Software Development Kit (SDK)
- Debug an application on-chip using the GNU debugger via SDK