Several fixes in the lib and notebook

[stefan-ba]

Changes / Fixes to the SPYN-Lib:
I added an init_mode. In this mode the motor turns slowly backwards in order to initialize the encoder ip. The encoder value gets always set to 0 so this fix will only work if the encoder is aligned with phase_a (should always be the case with EDPS).

Renamed the write registers 13 and 14 to DECIMATION and CAP_TRIGGER since they are only used as FA and FB in the SDSoC version of EDDP and I think the decimation feature in the HLS version is more useful.

Commented out the write registers 13, 14 and 15 in the set_mode() method since they have nothing to do with the motor mode.

Renamed the motor_capture_modes to what they really capture in the right order.

Corrected the small offset <-> value confusion in motor_controller.py.
Fixes #9

Changed the CAPTURE_VD_VQ_ANGLE from 6 to 3 (6 captures the PWM-Voltage not Vd/Vq)

Changes / Fixes to the SPYN-Notebook:
Removed the call of overlay.download() since it is automatically downloaded with the Overlay() call.

I run the init-mode for 4 seconds in order to initialize the encoder IP.

Decreased the capture_count to 128 since the stream data fifo in the overlay is only 4096 (128*32) samples wide.

Introduced the variable decimation to capture a bigger time frame when needed.

Then I first set the 'Data hold'-Bit with write_capturereg(0, 2) and wait until the FIFO is full. This is especially important with big decimation values because the FIFO might be read out faster than it is being filled.

With my setup I always get an offset on my adc values of Ia and Ib. I'm not sure why but it can be fixed if you just deduct this constant offset before further processing. In my case there's an offset of 245 and 140, respectively. In the "SPYN Quick Take Demo" Video they also seem to have 245 for Ia but less than 140 for Ib. In EDDP-FOC this offset is coreected by the "Filters" IP.

After the Capture is done it is important to reset the capture unit with write_capturereg(0,0). Otherwise the next capture wont execute properly.

Changes / Fixes to the Vivado-Project/Overlay:
As I mentioned I used the HSL version of EDDP in order to utilize the decimation feature. I had to change the Axis-Stream-Monitor IP so that it's valid signal is only set to '1', if both the valid and the ready signal of the monitored bus are also '1'. This way only actually transferred signals are being monitored and captured. The broadcaster IP between Angle_RPM_Ib_Ia-Concat and the monitor has to be removed and the signal can be monitored directly.
I can provide the Vivado projects, if desired.

I tested the overlays for the ARTY-Z7 and PYNQ-Z1. For PYNQ-Z2 I created the overlay, but couldn't test it because I have no access to a board. For the Ultra96 I didn't create an overlay yet. But also with the original overlay everything except the decimation will work.