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[XDP] Multiple CRs - fixed PLIO verification and refined all_stalls_s2mm metric set #8429

Merged
merged 7 commits into from
Sep 18, 2024
Merged

[XDP] Multiple CRs - fixed PLIO verification and refined all_stalls_s2mm metric set #8429

merged 7 commits into from
Sep 18, 2024

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pgschuey
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Problem solved by the commit

  • PLIOs were always getting traced, regardless of settings
  • The all_stalls_s2mm metric set should use individual stalls

How problem was solved, alternative solutions (if any) and why they were rejected

  • Verify stream IDs on PLIO match what's specified
  • In all_stalls_s2mm set, remove group stalls and only add cascade stalls on AIE2+

Risks (if any) associated the changes in the commit

  • The all_stalls_s2mm metric set no longer traces cascade stalls on AIE1

What has been tested and how, request additional testing if necessary

  • Tested on vck190 and vek280

Documentation impact (if any)

  • Change documentation of all_stalls_s2mm metric set (AIE1 only)

Paul Schumacher added 5 commits September 16, 2024 09:37
updates to all_stalls_s2mm/mm2s and comment
1104a17 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
corrected bug
4e711cb 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
fixed bug in identifying PLIO
ea86ac6 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
cleaned up IO identification
62b326e 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
final cleanup
69bc72f 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
@pgschuey pgschuey requested review from vipangul and removed request for jvillarre September 18, 2024 00:04
removed intrusive debug message
38aee34 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
@pgschuey
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retest please

small comment change
fecbbfb 
Signed-off-by: Paul Schumacher <schuey@xilinx.com>
@jvillarre jvillarre merged commit 53775ee into Xilinx:master Sep 18, 2024
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@jvillarre jvillarre jvillarre approved these changes

@vipangul vipangul vipangul approved these changes

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3 participants
@pgschuey @jvillarre @vipangul