Add aievec dialect, associated optimizations, and aievec-to-cpp transl… #81
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…ation. This allows generation of autovectorized AIE kernels from scalar kernels written in affine dialect
stephenneuendorffer
approved these changes
Jan 26, 2022
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| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| // (c) Copyright 2022 Xilinx Inc. | ||
| // |
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This is not part of the LLVM project. Please use the copyright in the mlir-aie repo
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| inline VectorType getVectorType(Value val) { | ||
| assert(val.getType().isa<VectorType>()); | ||
| return val.getType().cast<VectorType>(); | ||
| } |
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| Type getLHSType() { return lhs().getType(); } | ||
| Type getRHSType() { return rhs().getType(); } | ||
| Type getResultType() { return result().getType(); } | ||
| }]; |
| Results<(outs AIEVec_Acc:$result)> { | ||
| let summary = "AIE ups"; | ||
| let description = [{ | ||
| Xilinx-specific ups intrinsic. Moves data from AIE vector data type |
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ups -> upshift
| }]; | ||
| let extraClassDeclaration = [{ | ||
| size_t getSourceSize() { return sources().size(); } | ||
| Type getSourceType() { return sources().getTypes().front(); } |
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What requires the types to be the same?
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| if (!resultType) | ||
| return upd.emitError("requires vector type"); |
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Should come from tablegen?
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| if (result.attributes.getAttrs().size() != 1) | ||
| return parser.emitError(typesLoc, "requires one attribute"); | ||
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| // Assert that there are two types (source vector and accumulator result) | ||
| if (types.size() != 2) | ||
| return parser.emitError(typesLoc, "requires two types"); |
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This kind of thing should come from the tablegen spec.
lib/Dialect/AIEVec/IR/AIEVecOps.cpp
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| VectorType vectorType = types[0].dyn_cast<VectorType>(); | ||
| if (!vectorType) | ||
| return parser.emitError(typesLoc, "requires vector type"); | ||
| aievec::AccType accType = types[1].dyn_cast<aievec::AccType>(); | ||
| if (!accType) | ||
| return parser.emitError(typesLoc, "requires accumulator type"); |
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should come from tablegen
lib/Dialect/AIEVec/IR/AIEVecOps.cpp
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| if (IntegerType itype = ltype.dyn_cast<IntegerType>()) | ||
| ltypeWidth = itype.getWidth(); | ||
| else if (FloatType ftype = ltype.dyn_cast<FloatType>()) | ||
| ltypeWidth = ftype.getWidth(); | ||
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| if (IntegerType itype = rtype.dyn_cast<IntegerType>()) | ||
| rtypeWidth = itype.getWidth(); | ||
| else if (FloatType ftype = rtype.dyn_cast<FloatType>()) | ||
| rtypeWidth = ftype.getWidth(); | ||
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| if (IntegerType itype = atype.dyn_cast<IntegerType>()) | ||
| atypeWidth = itype.getWidth(); | ||
| else if (FloatType ftype = atype.dyn_cast<FloatType>()) | ||
| atypeWidth = ftype.getWidth(); | ||
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| if (ltypeWidth == 0 || rtypeWidth == 0 || atypeWidth == 0) | ||
| return mul.emitError("failed to find width of the vector or accumulator"); |
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Lots of duplication here.
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| bool isMulOrFMAOp = isa<MulIOp, MulFOp, vector::FMAOp>(Op); | ||
| bool isSubOrAddOp = isa<SubIOp, SubFOp, AddIOp, AddFOp>(Op); | ||
| if (!isMulOrFMAOp && !isSubOrAddOp) | ||
| return true; | ||
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This could be an MLIR trait?
pssrawat
changed the title
…e vecs must have same size
auto-merge was automatically disabled
January 27, 2022 21:14
Head branch was pushed to by a user without write access
fifield
added a commit
to fifield/mlir-aie
that referenced
this pull request
Nov 8, 2023
* Add addWeighted placeholder kernel test * Enable add_weighted_v0 rtp
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…ation. This allows generation of autovectorized AIE kernels from scalar kernels written in affine dialect