Hello,
This is Yashaswini M,
Pursuing Electronics and Communication Engineering at MS Ramaiah Institute Of Technology.
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MSRIT
- Bengaluru
- in/yashaswini-m-331a632b6
Popular repositories Loading
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Synchronous_FIFO_
Synchronous_FIFO_ PublicThis repo has complete testbench architecture for Synchronous FIFO(First in First Out ) basically a queue, tested using EDA playground
SystemVerilog
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HF24-LoLCode
HF24-LoLCode PublicForked from hackfest-dev/HF24-LoLCode
Hackfest Repository - HF24-LoLCode
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