![github-actions[bot]](https://avatars.githubusercontent.com/in/15368?v=4&size=40){kind=avatar}
1 file changed
+1
-1
lines changed- Makefile+1-1
- backends/verilog/verilog_backend.cc+134-252
- frontends/ast/simplify.cc+47-17
- frontends/verific/verific.cc+3-1
- kernel/ff.h+46
- kernel/ffinit.h+19-24
- passes/equiv/equiv_induct.cc+3-1
- passes/opt/Makefile.inc+1
- passes/opt/opt.cc+5-5
- passes/opt/opt_dff.cc+875
- passes/opt/opt_expr.cc+10-10
- passes/pmgen/ice40_dsp.cc+20-18
- passes/pmgen/ice40_dsp.pmg+66-229
- passes/pmgen/xilinx_dsp.cc+71-88
- passes/pmgen/xilinx_dsp.pmg+48-285
- passes/pmgen/xilinx_dsp48a.pmg+39-283
- passes/pmgen/xilinx_dsp_CREG.pmg+18-104
- passes/pmgen/xilinx_dsp_cascade.pmg+24-101
- passes/sat/async2sync.cc+159-101
- passes/sat/clk2fflogic.cc+3-44
- passes/techmap/Makefile.inc+1
- passes/techmap/dffunmap.cc+107
- techlibs/greenpak4/synth_greenpak4.cc+1-1
- techlibs/ice40/Makefile.inc-1
- techlibs/ice40/ice40_ffssr.cc-131
- techlibs/ice40/ice40_opt.cc+2-2
- techlibs/ice40/synth_ice40.cc+4-8
- techlibs/intel_alm/Makefile.inc+3-3
- techlibs/intel_alm/common/bram_m10k.txt+2-2
- techlibs/intel_alm/common/bram_m10k_map.v-31
- techlibs/intel_alm/common/megafunction_bb.v+36-1
- techlibs/intel_alm/common/mem_sim.v+34
- techlibs/intel_alm/common/quartus_rename.v+50-1
- techlibs/intel_alm/synth_intel_alm.cc+3-2
- techlibs/xilinx/synth_xilinx.cc+13-18
- tests/arch/ice40/fsm.ys+1-1
- tests/arch/intel_alm/blockram.ys+6
- tests/arch/intel_alm/mux.ys+6-6
- tests/arch/xilinx/fsm.ys+7-9
- tests/arch/xilinx/latches.ys+1-2
- tests/opt/bug2311.ys+14
- tests/opt/opt_dff_arst.ys+101
- tests/opt/opt_dff_clk.ys+45
- tests/opt/opt_dff_const.ys+49
- tests/opt/opt_dff_en.ys+157
- tests/opt/opt_dff_mux.ys+86
- tests/opt/opt_dff_qd.ys+56
- tests/opt/opt_dff_sr.ys+304
- tests/opt/opt_dff_srst.ys+113
- tests/opt/opt_rmdff.ys+1-1
- tests/opt/opt_rmdff_sat.ys+2-2
- tests/techmap/dffunmap.ys+100
- tests/various/const_arg_loop.v+44
- tests/various/const_arg_loop.ys+1
- tests/various/equiv_opt_undef.ys+35
0 commit comments