icebram: Found some bitslices up to 1 times, others only 0 times!

[SoerenSofke]

I like to initialize memory and subsitute it after synthesis by instrumenting icebram

reg [31:0] rom_memory [0:1023];

`ifdef SIMULATION
    initial $readmemh("mem_increment.hex", rom_memory);
`else
    initial $readmemh("mem_random.hex", rom_memory);
`endif

The following command issues an error

icebram mem_random.hex mem_increment.hex < build/$(PROJECT).asc > build/$(PROJECT)_reprogrammed.asc

and here is the error

Found some bitslices up to 1 times, others only 0 times! 

How should I proceed?

[SoerenSofke]

Meanwhile I figured out, that yosys or how I instrument it might be responsible for my finding with icebram

5.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing rom_top.rom_wb_inst.rom_memory:
Properties: ports=1 bits=32768 rports=1 wports=0 dbits=32 abits=10 words=1024
Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
Bram geometry: abits=8 dbits=16 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
Read port #0 is in clock domain \clk.
Mapped to bram port A1.1.
Updated properties: dups=1 waste=0 efficiency=100
Storing for later selection.
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
Bram geometry: abits=9 dbits=8 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
Read port #0 is in clock domain \clk.
Mapped to bram port A1.1.
Updated properties: dups=1 waste=0 efficiency=100
Storing for later selection.
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
Bram geometry: abits=10 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
Read port #0 is in clock domain \clk.
Mapped to bram port A1.1.
Updated properties: dups=1 waste=0 efficiency=100
Storing for later selection.
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
Bram geometry: abits=11 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ICE40_RAM4K_M123: awaste=1024 dwaste=0 bwaste=2048 waste=2048 efficiency=50
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
Read port #0 is in clock domain \clk.
Mapped to bram port A1.1.
Updated properties: dups=1 waste=2048 efficiency=50
Storing for later selection.
Selecting best of 4 rules:
Efficiency for rule 2.3: efficiency=50, cells=16, acells=1
Efficiency for rule 2.2: efficiency=100, cells=8, acells=1
Efficiency for rule 2.1: efficiency=100, cells=8, acells=2
Efficiency for rule 1.1: efficiency=100, cells=8, acells=4
Selected rule 2.2 with efficiency 100.
Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
Read port #0 is in clock domain \clk.
Mapped to bram port A1.1.
Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: rom_wb_inst.rom_memory.0.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <1 0 0>: rom_wb_inst.rom_memory.1.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <2 0 0>: rom_wb_inst.rom_memory.2.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <3 0 0>: rom_wb_inst.rom_memory.3.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <4 0 0>: rom_wb_inst.rom_memory.4.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <5 0 0>: rom_wb_inst.rom_memory.5.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <6 0 0>: rom_wb_inst.rom_memory.6.0.0
Creating $__ICE40_RAM4K_M123 cell at grid position <7 0 0>: rom_wb_inst.rom_memory.7.0.0

But finally, only a single SB_RAM40_4K is used, not 8.

=== rom_top ===
Number of wires: 23
Number of wire bits: 264
Number of public wires: 16
Number of public wire bits: 149
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 51
SB_CARRY 8
SB_DFF 16
SB_DFFSR 1
SB_LFOSC 1
SB_LUT4 24
SB_RAM40_4K 1

As you can see, the following instances are removed by the optimizer

5.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \rom_top..
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.6.0.0'.
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.5.0.0'.
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.4.0.0'.
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.1.0.0'.
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.3.0.0'.
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.2.0.0'.
removing unused \SB_RAM40_4K' cell \rom_wb_inst.rom_memory.7.0.0'.

[SoerenSofke]

As mentioned, Yosys is removing some RAM instances for optimization purpose. That is absolutely in line with the behavioral model. When I really make use of all the data in RAM, not optimization is performed and I can instrument icebram as anticipated.

Problem solved!