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read_ilang: allow slicing all sigspecs, not just wires #741

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merged 1 commit into from
Dec 17, 2018

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Accepting sigspec [n:m] is (a) a natural counterpart to accepting { sigspec1 sigspec2 }, (b) easily expressible via operations on RTLIL::SigSpec, and (c) not easily expressible outside of Yosys.

I am hitting the need for this while generating RTLIL in nMigen. I could probably work around it without the Yosys patch but it would be very ugly. Also, the new code is actually simpler!

whitequark added a commit to m-labs/nmigen that referenced this pull request Dec 16, 2018
@whitequark whitequark changed the title read_ilang: allow slicing sigspecs read_ilang: allow slicing all sigspecs, not just wires Dec 16, 2018
@cliffordwolf cliffordwolf merged commit 97b49d6 into YosysHQ:master Dec 17, 2018
@whitequark whitequark deleted the ilang_slice_sigspec branch December 17, 2018 15:29
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