rvc_asap

riscv-core-as-fast-as-passible

A single cycle riscv compatible with RV32I unprivileged spec.
https://riscv.org/technical/specifications/

In this project we will try to create a riscv core ASAP.

1. Follow the "HOW_TO" in the
2. Read spec.
3. Design block diagram.
4. Write SystemVerilog Core (RTL)
5. Write a TB. (validation & Stimuli)
6. Write c/assembly program to run on the core.

To builed the design - run the commad:

./buildl.sh all